3977 	radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) |  in cik_fence_gfx_ring_emit()
3989 	radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2));  in cik_fence_gfx_ring_emit()
4017 	radeon_ring_write(ring, upper_32_bits(addr));  in cik_fence_compute_ring_emit()
4043 	radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);  in cik_semaphore_ring_emit()
4105 		radeon_ring_write(ring, upper_32_bits(src_offset));  in cik_copy_cpdma()
4107 		radeon_ring_write(ring, upper_32_bits(dst_offset));  in cik_copy_cpdma()
4166 			radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));  in cik_ring_ib_execute()
4177 	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);  in cik_ring_ib_execute()
4498 	WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);  in cik_cp_gfx_resume()
4511 	WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr));  in cik_cp_gfx_resume()
4956 	WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);  in cik_cp_compute_resume()
5055 		mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);  in cik_cp_compute_resume()
5066 		mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);  in cik_cp_compute_resume()
5094 		mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;  in cik_cp_compute_resume()
5106 			upper_32_bits(wb_gpu_addr) & 0xffff;  in cik_cp_compute_resume()
7063 		WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr));  in cik_init_gfx_cgpg()
7425 	WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);  in cik_irq_init()