6241 static void cik_update_rlc(struct radeon_device *rdev, u32 rlc)  in cik_update_rlc()  argument
6246 	if (tmp != rlc)  in cik_update_rlc()
6247 		WREG32(RLC_CNTL, rlc);  in cik_update_rlc()
6863 	if (rdev->rlc.cp_table_ptr == NULL)  in cik_init_cp_pg_table()
6867 	dst_ptr = rdev->rlc.cp_table_ptr;  in cik_init_cp_pg_table()
7061 	if (rdev->rlc.cs_data) {  in cik_init_gfx_cgpg()
7063 		WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr));  in cik_init_gfx_cgpg()
7064 		WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr));  in cik_init_gfx_cgpg()
7065 		WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size);  in cik_init_gfx_cgpg()
7071 	if (rdev->rlc.reg_list) {  in cik_init_gfx_cgpg()
7073 		for (i = 0; i < rdev->rlc.reg_list_size; i++)  in cik_init_gfx_cgpg()
7074 			WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]);  in cik_init_gfx_cgpg()
7082 	WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);  in cik_init_gfx_cgpg()
7083 	WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8);  in cik_init_gfx_cgpg()
7118 	if (rdev->rlc.cs_data == NULL)  in cik_get_csb_size()
7126 	for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {  in cik_get_csb_size()
7150 	if (rdev->rlc.cs_data == NULL)  in cik_get_csb_buffer()
7162 	for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {  in cik_get_csb_buffer()
8535 			rdev->rlc.reg_list = spectre_rlc_save_restore_register_list;  in cik_startup()
8536 			rdev->rlc.reg_list_size =  in cik_startup()
8539 			rdev->rlc.reg_list = kalindi_rlc_save_restore_register_list;  in cik_startup()
8540 			rdev->rlc.reg_list_size =  in cik_startup()
8544 	rdev->rlc.cs_data = ci_cs_data;  in cik_startup()
8545 	rdev->rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4;  in cik_startup()