Lines Matching refs:ring
3867 int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) in cik_ring_test() argument
3880 r = radeon_ring_lock(rdev, ring, 3); in cik_ring_test()
3882 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); in cik_ring_test()
3886 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_test()
3887 radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2)); in cik_ring_test()
3888 radeon_ring_write(ring, 0xDEADBEEF); in cik_ring_test()
3889 radeon_ring_unlock_commit(rdev, ring, false); in cik_ring_test()
3898 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); in cik_ring_test()
3901 ring->idx, scratch, tmp); in cik_ring_test()
3919 struct radeon_ring *ring = &rdev->ring[ridx]; in cik_hdp_flush_cp_ring_emit() local
3922 switch (ring->idx) { in cik_hdp_flush_cp_ring_emit()
3926 switch (ring->me) { in cik_hdp_flush_cp_ring_emit()
3928 ref_and_mask = CP2 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3931 ref_and_mask = CP6 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3942 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_hdp_flush_cp_ring_emit()
3943 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ in cik_hdp_flush_cp_ring_emit()
3946 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2); in cik_hdp_flush_cp_ring_emit()
3947 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2); in cik_hdp_flush_cp_ring_emit()
3948 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3949 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3950 radeon_ring_write(ring, 0x20); /* poll interval */ in cik_hdp_flush_cp_ring_emit()
3965 struct radeon_ring *ring = &rdev->ring[fence->ring]; in cik_fence_gfx_ring_emit() local
3966 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_fence_gfx_ring_emit()
3971 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3972 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_gfx_ring_emit()
3976 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_gfx_ring_emit()
3977 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in cik_fence_gfx_ring_emit()
3979 radeon_ring_write(ring, fence->seq - 1); in cik_fence_gfx_ring_emit()
3980 radeon_ring_write(ring, 0); in cik_fence_gfx_ring_emit()
3983 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3984 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_gfx_ring_emit()
3988 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_gfx_ring_emit()
3989 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2)); in cik_fence_gfx_ring_emit()
3990 radeon_ring_write(ring, fence->seq); in cik_fence_gfx_ring_emit()
3991 radeon_ring_write(ring, 0); in cik_fence_gfx_ring_emit()
4006 struct radeon_ring *ring = &rdev->ring[fence->ring]; in cik_fence_compute_ring_emit() local
4007 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_fence_compute_ring_emit()
4010 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in cik_fence_compute_ring_emit()
4011 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_compute_ring_emit()
4015 radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2)); in cik_fence_compute_ring_emit()
4016 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_compute_ring_emit()
4017 radeon_ring_write(ring, upper_32_bits(addr)); in cik_fence_compute_ring_emit()
4018 radeon_ring_write(ring, fence->seq); in cik_fence_compute_ring_emit()
4019 radeon_ring_write(ring, 0); in cik_fence_compute_ring_emit()
4034 struct radeon_ring *ring, in cik_semaphore_ring_emit() argument
4041 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in cik_semaphore_ring_emit()
4042 radeon_ring_write(ring, lower_32_bits(addr)); in cik_semaphore_ring_emit()
4043 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); in cik_semaphore_ring_emit()
4045 if (emit_wait && ring->idx == RADEON_RING_TYPE_GFX_INDEX) { in cik_semaphore_ring_emit()
4047 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_semaphore_ring_emit()
4048 radeon_ring_write(ring, 0x0); in cik_semaphore_ring_emit()
4075 struct radeon_ring *ring = &rdev->ring[ring_index]; in cik_copy_cpdma() local
4084 r = radeon_ring_lock(rdev, ring, num_loops * 7 + 18); in cik_copy_cpdma()
4092 radeon_sync_rings(rdev, &sync, ring->idx); in cik_copy_cpdma()
4102 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in cik_copy_cpdma()
4103 radeon_ring_write(ring, control); in cik_copy_cpdma()
4104 radeon_ring_write(ring, lower_32_bits(src_offset)); in cik_copy_cpdma()
4105 radeon_ring_write(ring, upper_32_bits(src_offset)); in cik_copy_cpdma()
4106 radeon_ring_write(ring, lower_32_bits(dst_offset)); in cik_copy_cpdma()
4107 radeon_ring_write(ring, upper_32_bits(dst_offset)); in cik_copy_cpdma()
4108 radeon_ring_write(ring, cur_size_in_bytes); in cik_copy_cpdma()
4113 r = radeon_fence_emit(rdev, &fence, ring->idx); in cik_copy_cpdma()
4115 radeon_ring_unlock_undo(rdev, ring); in cik_copy_cpdma()
4120 radeon_ring_unlock_commit(rdev, ring, false); in cik_copy_cpdma()
4143 struct radeon_ring *ring = &rdev->ring[ib->ring]; in cik_ring_ib_execute() local
4144 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0; in cik_ring_ib_execute()
4149 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in cik_ring_ib_execute()
4150 radeon_ring_write(ring, 0); in cik_ring_ib_execute()
4155 if (ring->rptr_save_reg) { in cik_ring_ib_execute()
4156 next_rptr = ring->wptr + 3 + 4; in cik_ring_ib_execute()
4157 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_ib_execute()
4158 radeon_ring_write(ring, ((ring->rptr_save_reg - in cik_ring_ib_execute()
4160 radeon_ring_write(ring, next_rptr); in cik_ring_ib_execute()
4162 next_rptr = ring->wptr + 5 + 4; in cik_ring_ib_execute()
4163 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_ring_ib_execute()
4164 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()
4165 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in cik_ring_ib_execute()
4166 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in cik_ring_ib_execute()
4167 radeon_ring_write(ring, next_rptr); in cik_ring_ib_execute()
4175 radeon_ring_write(ring, header); in cik_ring_ib_execute()
4176 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFFC)); in cik_ring_ib_execute()
4177 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in cik_ring_ib_execute()
4178 radeon_ring_write(ring, control); in cik_ring_ib_execute()
4191 int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) in cik_ib_test() argument
4205 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); in cik_ib_test()
4236 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); in cik_ib_test()
4286 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cik_cp_gfx_enable()
4388 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cik_cp_gfx_start() local
4398 r = radeon_ring_lock(rdev, ring, cik_default_size + 17); in cik_cp_gfx_start()
4405 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in cik_cp_gfx_start()
4406 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in cik_cp_gfx_start()
4407 radeon_ring_write(ring, 0x8000); in cik_cp_gfx_start()
4408 radeon_ring_write(ring, 0x8000); in cik_cp_gfx_start()
4411 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cik_cp_gfx_start()
4412 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cik_cp_gfx_start()
4414 radeon_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in cik_cp_gfx_start()
4415 radeon_ring_write(ring, 0x80000000); in cik_cp_gfx_start()
4416 radeon_ring_write(ring, 0x80000000); in cik_cp_gfx_start()
4419 radeon_ring_write(ring, cik_default_state[i]); in cik_cp_gfx_start()
4421 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cik_cp_gfx_start()
4422 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_cp_gfx_start()
4425 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cik_cp_gfx_start()
4426 radeon_ring_write(ring, 0); in cik_cp_gfx_start()
4428 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in cik_cp_gfx_start()
4429 radeon_ring_write(ring, 0x00000316); in cik_cp_gfx_start()
4430 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ in cik_cp_gfx_start()
4431 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ in cik_cp_gfx_start()
4433 radeon_ring_unlock_commit(rdev, ring, false); in cik_cp_gfx_start()
4449 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in cik_cp_gfx_fini()
4463 struct radeon_ring *ring; in cik_cp_gfx_resume() local
4483 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cik_cp_gfx_resume()
4484 rb_bufsz = order_base_2(ring->ring_size / 8); in cik_cp_gfx_resume()
4493 ring->wptr = 0; in cik_cp_gfx_resume()
4494 WREG32(CP_RB0_WPTR, ring->wptr); in cik_cp_gfx_resume()
4509 rb_addr = ring->gpu_addr >> 8; in cik_cp_gfx_resume()
4515 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; in cik_cp_gfx_resume()
4516 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in cik_cp_gfx_resume()
4518 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cik_cp_gfx_resume()
4529 struct radeon_ring *ring) in cik_gfx_get_rptr() argument
4534 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cik_gfx_get_rptr()
4542 struct radeon_ring *ring) in cik_gfx_get_wptr() argument
4552 struct radeon_ring *ring) in cik_gfx_set_wptr() argument
4554 WREG32(CP_RB0_WPTR, ring->wptr); in cik_gfx_set_wptr()
4559 struct radeon_ring *ring) in cik_compute_get_rptr() argument
4564 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cik_compute_get_rptr()
4567 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0); in cik_compute_get_rptr()
4577 struct radeon_ring *ring) in cik_compute_get_wptr() argument
4583 wptr = rdev->wb.wb[ring->wptr_offs/4]; in cik_compute_get_wptr()
4586 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0); in cik_compute_get_wptr()
4596 struct radeon_ring *ring) in cik_compute_set_wptr() argument
4599 rdev->wb.wb[ring->wptr_offs/4] = ring->wptr; in cik_compute_set_wptr()
4600 WDOORBELL32(ring->doorbell_index, ring->wptr); in cik_compute_set_wptr()
4604 struct radeon_ring *ring) in cik_compute_stop() argument
4608 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0); in cik_compute_stop()
4646 cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]); in cik_cp_compute_enable()
4647 cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]); in cik_cp_compute_enable()
4651 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cik_cp_compute_enable()
4652 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cik_cp_compute_enable()
4763 if (rdev->ring[idx].mqd_obj) { in cik_cp_compute_fini()
4764 r = radeon_bo_reserve(rdev->ring[idx].mqd_obj, false); in cik_cp_compute_fini()
4768 radeon_bo_unpin(rdev->ring[idx].mqd_obj); in cik_cp_compute_fini()
4769 radeon_bo_unreserve(rdev->ring[idx].mqd_obj); in cik_cp_compute_fini()
4771 radeon_bo_unref(&rdev->ring[idx].mqd_obj); in cik_cp_compute_fini()
4772 rdev->ring[idx].mqd_obj = NULL; in cik_cp_compute_fini()
4976 if (rdev->ring[idx].mqd_obj == NULL) { in cik_cp_compute_resume()
4981 NULL, &rdev->ring[idx].mqd_obj); in cik_cp_compute_resume()
4988 r = radeon_bo_reserve(rdev->ring[idx].mqd_obj, false); in cik_cp_compute_resume()
4993 r = radeon_bo_pin(rdev->ring[idx].mqd_obj, RADEON_GEM_DOMAIN_GTT, in cik_cp_compute_resume()
5000 r = radeon_bo_kmap(rdev->ring[idx].mqd_obj, (void **)&buf); in cik_cp_compute_resume()
5018 cik_srbm_select(rdev, rdev->ring[idx].me, in cik_cp_compute_resume()
5019 rdev->ring[idx].pipe, in cik_cp_compute_resume()
5020 rdev->ring[idx].queue, 0); in cik_cp_compute_resume()
5064 hqd_gpu_addr = rdev->ring[idx].gpu_addr >> 8; in cik_cp_compute_resume()
5076 order_base_2(rdev->ring[idx].ring_size / 8); in cik_cp_compute_resume()
5118 DOORBELL_OFFSET(rdev->ring[idx].doorbell_index); in cik_cp_compute_resume()
5130 rdev->ring[idx].wptr = 0; in cik_cp_compute_resume()
5131 mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr; in cik_cp_compute_resume()
5146 radeon_bo_kunmap(rdev->ring[idx].mqd_obj); in cik_cp_compute_resume()
5147 radeon_bo_unreserve(rdev->ring[idx].mqd_obj); in cik_cp_compute_resume()
5149 rdev->ring[idx].ready = true; in cik_cp_compute_resume()
5150 r = radeon_ring_test(rdev, idx, &rdev->ring[idx]); in cik_cp_compute_resume()
5152 rdev->ring[idx].ready = false; in cik_cp_compute_resume()
5656 bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in cik_gfx_is_lockup() argument
5663 radeon_ring_lockup_update(rdev, ring); in cik_gfx_is_lockup()
5666 return radeon_ring_test_lockup(rdev, ring); in cik_gfx_is_lockup()
6110 void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, in cik_vm_flush() argument
6113 int usepfp = (ring->idx == RADEON_RING_TYPE_GFX_INDEX); in cik_vm_flush()
6115 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
6116 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6119 radeon_ring_write(ring, in cik_vm_flush()
6122 radeon_ring_write(ring, in cik_vm_flush()
6125 radeon_ring_write(ring, 0); in cik_vm_flush()
6126 radeon_ring_write(ring, pd_addr >> 12); in cik_vm_flush()
6129 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
6130 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6132 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); in cik_vm_flush()
6133 radeon_ring_write(ring, 0); in cik_vm_flush()
6134 radeon_ring_write(ring, VMID(vm_id)); in cik_vm_flush()
6136 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); in cik_vm_flush()
6137 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6139 radeon_ring_write(ring, SH_MEM_BASES >> 2); in cik_vm_flush()
6140 radeon_ring_write(ring, 0); in cik_vm_flush()
6142 radeon_ring_write(ring, 0); /* SH_MEM_BASES */ in cik_vm_flush()
6143 radeon_ring_write(ring, 0); /* SH_MEM_CONFIG */ in cik_vm_flush()
6144 radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */ in cik_vm_flush()
6145 radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ in cik_vm_flush()
6147 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
6148 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6150 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); in cik_vm_flush()
6151 radeon_ring_write(ring, 0); in cik_vm_flush()
6152 radeon_ring_write(ring, VMID(0)); in cik_vm_flush()
6155 cik_hdp_flush_cp_ring_emit(rdev, ring->idx); in cik_vm_flush()
6158 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
6159 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6161 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cik_vm_flush()
6162 radeon_ring_write(ring, 0); in cik_vm_flush()
6163 radeon_ring_write(ring, 1 << vm_id); in cik_vm_flush()
6166 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_vm_flush()
6167 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ in cik_vm_flush()
6170 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cik_vm_flush()
6171 radeon_ring_write(ring, 0); in cik_vm_flush()
6172 radeon_ring_write(ring, 0); /* ref */ in cik_vm_flush()
6173 radeon_ring_write(ring, 0); /* mask */ in cik_vm_flush()
6174 radeon_ring_write(ring, 0x20); /* poll interval */ in cik_vm_flush()
6179 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_vm_flush()
6180 radeon_ring_write(ring, 0x0); in cik_vm_flush()
7503 struct radeon_ring *ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in cik_irq_set() local
7505 if (ring->me == 1) { in cik_irq_set()
7506 switch (ring->pipe) { in cik_irq_set()
7511 DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe); in cik_irq_set()
7515 DRM_DEBUG("si_irq_set: sw int cp1 invalid me %d\n", ring->me); in cik_irq_set()
7519 struct radeon_ring *ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in cik_irq_set() local
7521 if (ring->me == 1) { in cik_irq_set()
7522 switch (ring->pipe) { in cik_irq_set()
7527 DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe); in cik_irq_set()
7531 DRM_DEBUG("si_irq_set: sw int cp2 invalid me %d\n", ring->me); in cik_irq_set()
7916 struct radeon_ring *cp1_ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in cik_irq_process()
7917 struct radeon_ring *cp2_ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in cik_irq_process()
7953 (const void *) &rdev->ih.ring[ring_index]); in cik_irq_process()
7955 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; in cik_irq_process()
7956 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; in cik_irq_process()
7957 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff; in cik_irq_process()
8503 struct radeon_ring *ring; in cik_startup() local
8605 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in cik_startup()
8619 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; in cik_startup()
8620 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; in cik_startup()
8647 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cik_startup()
8648 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in cik_startup()
8655 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in cik_startup()
8656 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET, in cik_startup()
8660 ring->me = 1; /* first MEC */ in cik_startup()
8661 ring->pipe = 0; /* first pipe */ in cik_startup()
8662 ring->queue = 0; /* first queue */ in cik_startup()
8663 ring->wptr_offs = CIK_WB_CP1_WPTR_OFFSET; in cik_startup()
8666 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in cik_startup()
8667 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET, in cik_startup()
8672 ring->me = 1; /* first MEC */ in cik_startup()
8673 ring->pipe = 0; /* first pipe */ in cik_startup()
8674 ring->queue = 1; /* second queue */ in cik_startup()
8675 ring->wptr_offs = CIK_WB_CP2_WPTR_OFFSET; in cik_startup()
8677 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cik_startup()
8678 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in cik_startup()
8683 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cik_startup()
8684 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, in cik_startup()
8697 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in cik_startup()
8698 if (ring->ring_size) { in cik_startup()
8699 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, in cik_startup()
8709 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; in cik_startup()
8710 if (ring->ring_size) in cik_startup()
8711 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, in cik_startup()
8714 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; in cik_startup()
8715 if (ring->ring_size) in cik_startup()
8716 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, in cik_startup()
8827 struct radeon_ring *ring; in cik_init() local
8900 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cik_init()
8901 ring->ring_obj = NULL; in cik_init()
8902 r600_ring_init(rdev, ring, 1024 * 1024); in cik_init()
8904 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in cik_init()
8905 ring->ring_obj = NULL; in cik_init()
8906 r600_ring_init(rdev, ring, 1024 * 1024); in cik_init()
8907 r = radeon_doorbell_get(rdev, &ring->doorbell_index); in cik_init()
8911 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in cik_init()
8912 ring->ring_obj = NULL; in cik_init()
8913 r600_ring_init(rdev, ring, 1024 * 1024); in cik_init()
8914 r = radeon_doorbell_get(rdev, &ring->doorbell_index); in cik_init()
8918 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cik_init()
8919 ring->ring_obj = NULL; in cik_init()
8920 r600_ring_init(rdev, ring, 256 * 1024); in cik_init()
8922 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cik_init()
8923 ring->ring_obj = NULL; in cik_init()
8924 r600_ring_init(rdev, ring, 256 * 1024); in cik_init()
8928 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in cik_init()
8929 ring->ring_obj = NULL; in cik_init()
8930 r600_ring_init(rdev, ring, 4096); in cik_init()
8935 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; in cik_init()
8936 ring->ring_obj = NULL; in cik_init()
8937 r600_ring_init(rdev, ring, 4096); in cik_init()
8939 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; in cik_init()
8940 ring->ring_obj = NULL; in cik_init()
8941 r600_ring_init(rdev, ring, 4096); in cik_init()