2348 	u32 reg_offset, gb_tile_moden, split_equal_to_row_size;  in cik_tiling_mode_table_init()  local
2371 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
2372 			switch (reg_offset) {  in cik_tiling_mode_table_init()
2497 			rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
2498 			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()
2500 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
2501 			switch (reg_offset) {  in cik_tiling_mode_table_init()
2590 			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
2591 			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()
2594 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
2595 			switch (reg_offset) {  in cik_tiling_mode_table_init()
2720 			rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
2721 			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()
2723 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
2724 			switch (reg_offset) {  in cik_tiling_mode_table_init()
2813 			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
2814 			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()
2818 			for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
2819 				switch (reg_offset) {  in cik_tiling_mode_table_init()
2944 				rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
2945 				WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()
2948 			for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
2949 				switch (reg_offset) {  in cik_tiling_mode_table_init()
3074 				rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
3075 				WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()
3078 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
3079 			switch (reg_offset) {  in cik_tiling_mode_table_init()
3168 			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
3169 			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()
3172 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
3173 			switch (reg_offset) {  in cik_tiling_mode_table_init()
3298 			rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
3299 			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()
3301 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
3302 			switch (reg_offset) {  in cik_tiling_mode_table_init()
3391 			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
3392 			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()