Lines Matching refs:radeon_ring_write
3886 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_test()
3887 radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2)); in cik_ring_test()
3888 radeon_ring_write(ring, 0xDEADBEEF); in cik_ring_test()
3942 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_hdp_flush_cp_ring_emit()
3943 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ in cik_hdp_flush_cp_ring_emit()
3946 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2); in cik_hdp_flush_cp_ring_emit()
3947 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2); in cik_hdp_flush_cp_ring_emit()
3948 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3949 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3950 radeon_ring_write(ring, 0x20); /* poll interval */ in cik_hdp_flush_cp_ring_emit()
3971 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3972 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_gfx_ring_emit()
3976 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_gfx_ring_emit()
3977 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in cik_fence_gfx_ring_emit()
3979 radeon_ring_write(ring, fence->seq - 1); in cik_fence_gfx_ring_emit()
3980 radeon_ring_write(ring, 0); in cik_fence_gfx_ring_emit()
3983 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3984 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_gfx_ring_emit()
3988 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_gfx_ring_emit()
3989 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2)); in cik_fence_gfx_ring_emit()
3990 radeon_ring_write(ring, fence->seq); in cik_fence_gfx_ring_emit()
3991 radeon_ring_write(ring, 0); in cik_fence_gfx_ring_emit()
4010 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in cik_fence_compute_ring_emit()
4011 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_compute_ring_emit()
4015 radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2)); in cik_fence_compute_ring_emit()
4016 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_compute_ring_emit()
4017 radeon_ring_write(ring, upper_32_bits(addr)); in cik_fence_compute_ring_emit()
4018 radeon_ring_write(ring, fence->seq); in cik_fence_compute_ring_emit()
4019 radeon_ring_write(ring, 0); in cik_fence_compute_ring_emit()
4041 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in cik_semaphore_ring_emit()
4042 radeon_ring_write(ring, lower_32_bits(addr)); in cik_semaphore_ring_emit()
4043 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); in cik_semaphore_ring_emit()
4047 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_semaphore_ring_emit()
4048 radeon_ring_write(ring, 0x0); in cik_semaphore_ring_emit()
4102 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in cik_copy_cpdma()
4103 radeon_ring_write(ring, control); in cik_copy_cpdma()
4104 radeon_ring_write(ring, lower_32_bits(src_offset)); in cik_copy_cpdma()
4105 radeon_ring_write(ring, upper_32_bits(src_offset)); in cik_copy_cpdma()
4106 radeon_ring_write(ring, lower_32_bits(dst_offset)); in cik_copy_cpdma()
4107 radeon_ring_write(ring, upper_32_bits(dst_offset)); in cik_copy_cpdma()
4108 radeon_ring_write(ring, cur_size_in_bytes); in cik_copy_cpdma()
4149 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in cik_ring_ib_execute()
4150 radeon_ring_write(ring, 0); in cik_ring_ib_execute()
4157 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_ib_execute()
4158 radeon_ring_write(ring, ((ring->rptr_save_reg - in cik_ring_ib_execute()
4160 radeon_ring_write(ring, next_rptr); in cik_ring_ib_execute()
4163 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_ring_ib_execute()
4164 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()
4165 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in cik_ring_ib_execute()
4166 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in cik_ring_ib_execute()
4167 radeon_ring_write(ring, next_rptr); in cik_ring_ib_execute()
4175 radeon_ring_write(ring, header); in cik_ring_ib_execute()
4176 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFFC)); in cik_ring_ib_execute()
4177 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in cik_ring_ib_execute()
4178 radeon_ring_write(ring, control); in cik_ring_ib_execute()
4405 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in cik_cp_gfx_start()
4406 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in cik_cp_gfx_start()
4407 radeon_ring_write(ring, 0x8000); in cik_cp_gfx_start()
4408 radeon_ring_write(ring, 0x8000); in cik_cp_gfx_start()
4411 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cik_cp_gfx_start()
4412 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cik_cp_gfx_start()
4414 radeon_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in cik_cp_gfx_start()
4415 radeon_ring_write(ring, 0x80000000); in cik_cp_gfx_start()
4416 radeon_ring_write(ring, 0x80000000); in cik_cp_gfx_start()
4419 radeon_ring_write(ring, cik_default_state[i]); in cik_cp_gfx_start()
4421 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cik_cp_gfx_start()
4422 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_cp_gfx_start()
4425 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cik_cp_gfx_start()
4426 radeon_ring_write(ring, 0); in cik_cp_gfx_start()
4428 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in cik_cp_gfx_start()
4429 radeon_ring_write(ring, 0x00000316); in cik_cp_gfx_start()
4430 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ in cik_cp_gfx_start()
4431 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ in cik_cp_gfx_start()
6115 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
6116 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6119 radeon_ring_write(ring, in cik_vm_flush()
6122 radeon_ring_write(ring, in cik_vm_flush()
6125 radeon_ring_write(ring, 0); in cik_vm_flush()
6126 radeon_ring_write(ring, pd_addr >> 12); in cik_vm_flush()
6129 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
6130 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6132 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); in cik_vm_flush()
6133 radeon_ring_write(ring, 0); in cik_vm_flush()
6134 radeon_ring_write(ring, VMID(vm_id)); in cik_vm_flush()
6136 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); in cik_vm_flush()
6137 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6139 radeon_ring_write(ring, SH_MEM_BASES >> 2); in cik_vm_flush()
6140 radeon_ring_write(ring, 0); in cik_vm_flush()
6142 radeon_ring_write(ring, 0); /* SH_MEM_BASES */ in cik_vm_flush()
6143 radeon_ring_write(ring, 0); /* SH_MEM_CONFIG */ in cik_vm_flush()
6144 radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */ in cik_vm_flush()
6145 radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ in cik_vm_flush()
6147 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
6148 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6150 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); in cik_vm_flush()
6151 radeon_ring_write(ring, 0); in cik_vm_flush()
6152 radeon_ring_write(ring, VMID(0)); in cik_vm_flush()
6158 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
6159 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6161 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cik_vm_flush()
6162 radeon_ring_write(ring, 0); in cik_vm_flush()
6163 radeon_ring_write(ring, 1 << vm_id); in cik_vm_flush()
6166 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_vm_flush()
6167 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ in cik_vm_flush()
6170 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cik_vm_flush()
6171 radeon_ring_write(ring, 0); in cik_vm_flush()
6172 radeon_ring_write(ring, 0); /* ref */ in cik_vm_flush()
6173 radeon_ring_write(ring, 0); /* mask */ in cik_vm_flush()
6174 radeon_ring_write(ring, 0x20); /* poll interval */ in cik_vm_flush()
6179 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_vm_flush()
6180 radeon_ring_write(ring, 0x0); in cik_vm_flush()