9021 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);  in dce8_program_fmt()  local
9077 	WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);  in dce8_program_fmt()
9094 				   struct radeon_crtc *radeon_crtc,  in dce8_line_buffer_adjust()  argument
9098 	u32 pipe_offset = radeon_crtc->crtc_id * 0x20;  in dce8_line_buffer_adjust()
9107 	if (radeon_crtc->base.enabled && mode) {  in dce8_line_buffer_adjust()
9127 	WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset,  in dce8_line_buffer_adjust()
9139 	if (radeon_crtc->base.enabled && mode) {  in dce8_line_buffer_adjust()
9536 				    struct radeon_crtc *radeon_crtc,  in dce8_program_watermarks()  argument
9539 	struct drm_display_mode *mode = &radeon_crtc->base.mode;  in dce8_program_watermarks()
9546 	if (radeon_crtc->base.enabled && num_heads && mode) {  in dce8_program_watermarks()
9569 		wm_high.vsc = radeon_crtc->vsc;  in dce8_program_watermarks()
9571 		if (radeon_crtc->rmx_type != RMX_OFF)  in dce8_program_watermarks()
9609 		wm_low.vsc = radeon_crtc->vsc;  in dce8_program_watermarks()
9611 		if (radeon_crtc->rmx_type != RMX_OFF)  in dce8_program_watermarks()
9631 		radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);  in dce8_program_watermarks()
9635 	wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);  in dce8_program_watermarks()
9639 	WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);  in dce8_program_watermarks()
9640 	WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,  in dce8_program_watermarks()
9644 	tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);  in dce8_program_watermarks()
9647 	WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);  in dce8_program_watermarks()
9648 	WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,  in dce8_program_watermarks()
9652 	WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);  in dce8_program_watermarks()
9655 	radeon_crtc->line_time = line_time;  in dce8_program_watermarks()
9656 	radeon_crtc->wm_high = latency_watermark_a;  in dce8_program_watermarks()
9657 	radeon_crtc->wm_low = latency_watermark_b;  in dce8_program_watermarks()