4912 	struct hqd_registers queue_state;  member
5028 		mqd->queue_state.cp_hqd_pq_doorbell_control =  in cik_cp_compute_resume()
5031 			mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;  in cik_cp_compute_resume()
5033 			mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_EN;  in cik_cp_compute_resume()
5035 		       mqd->queue_state.cp_hqd_pq_doorbell_control);  in cik_cp_compute_resume()
5038 		mqd->queue_state.cp_hqd_dequeue_request = 0;  in cik_cp_compute_resume()
5039 		mqd->queue_state.cp_hqd_pq_rptr = 0;  in cik_cp_compute_resume()
5040 		mqd->queue_state.cp_hqd_pq_wptr= 0;  in cik_cp_compute_resume()
5048 			WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);  in cik_cp_compute_resume()
5049 			WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);  in cik_cp_compute_resume()
5050 			WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);  in cik_cp_compute_resume()
5054 		mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;  in cik_cp_compute_resume()
5055 		mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);  in cik_cp_compute_resume()
5056 		WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);  in cik_cp_compute_resume()
5057 		WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);  in cik_cp_compute_resume()
5059 		mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL);  in cik_cp_compute_resume()
5060 		mqd->queue_state.cp_mqd_control &= ~MQD_VMID_MASK;  in cik_cp_compute_resume()
5061 		WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);  in cik_cp_compute_resume()
5065 		mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;  in cik_cp_compute_resume()
5066 		mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);  in cik_cp_compute_resume()
5067 		WREG32(CP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);  in cik_cp_compute_resume()
5068 		WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);  in cik_cp_compute_resume()
5071 		mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);  in cik_cp_compute_resume()
5072 		mqd->queue_state.cp_hqd_pq_control &=  in cik_cp_compute_resume()
5075 		mqd->queue_state.cp_hqd_pq_control |=  in cik_cp_compute_resume()
5077 		mqd->queue_state.cp_hqd_pq_control |=  in cik_cp_compute_resume()
5080 		mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT;  in cik_cp_compute_resume()
5082 		mqd->queue_state.cp_hqd_pq_control &=  in cik_cp_compute_resume()
5084 		mqd->queue_state.cp_hqd_pq_control |=  in cik_cp_compute_resume()
5086 		WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);  in cik_cp_compute_resume()
5093 		mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;  in cik_cp_compute_resume()
5094 		mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;  in cik_cp_compute_resume()
5095 		WREG32(CP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);  in cik_cp_compute_resume()
5097 		       mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);  in cik_cp_compute_resume()
5104 		mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;  in cik_cp_compute_resume()
5105 		mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =  in cik_cp_compute_resume()
5108 		       mqd->queue_state.cp_hqd_pq_rptr_report_addr);  in cik_cp_compute_resume()
5110 		       mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);  in cik_cp_compute_resume()
5114 			mqd->queue_state.cp_hqd_pq_doorbell_control =  in cik_cp_compute_resume()
5116 			mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_OFFSET_MASK;  in cik_cp_compute_resume()
5117 			mqd->queue_state.cp_hqd_pq_doorbell_control |=  in cik_cp_compute_resume()
5119 			mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;  in cik_cp_compute_resume()
5120 			mqd->queue_state.cp_hqd_pq_doorbell_control &=  in cik_cp_compute_resume()
5124 			mqd->queue_state.cp_hqd_pq_doorbell_control = 0;  in cik_cp_compute_resume()
5127 		       mqd->queue_state.cp_hqd_pq_doorbell_control);  in cik_cp_compute_resume()
5131 		mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr;  in cik_cp_compute_resume()
5132 		WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);  in cik_cp_compute_resume()
5133 		mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR);  in cik_cp_compute_resume()
5136 		mqd->queue_state.cp_hqd_vmid = 0;  in cik_cp_compute_resume()
5137 		WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);  in cik_cp_compute_resume()
5140 		mqd->queue_state.cp_hqd_active = 1;  in cik_cp_compute_resume()
5141 		WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);  in cik_cp_compute_resume()