3966 	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;  in cik_fence_gfx_ring_emit()
4007 	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;  in cik_fence_compute_ring_emit()
4038 	uint64_t addr = semaphore->gpu_addr;  in cik_semaphore_ring_emit()
4176 	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFFC));  in cik_ring_ib_execute()
4177 	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);  in cik_ring_ib_execute()
4479 	WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);  in cik_cp_gfx_resume()
4497 	WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);  in cik_cp_gfx_resume()
4498 	WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);  in cik_cp_gfx_resume()
4509 	rb_addr = ring->gpu_addr >> 8;  in cik_cp_gfx_resume()
5064 		hqd_gpu_addr = rdev->ring[idx].gpu_addr >> 8;  in cik_cp_compute_resume()
5090 			wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP1_WPTR_OFFSET;  in cik_cp_compute_resume()
5092 			wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP2_WPTR_OFFSET;  in cik_cp_compute_resume()
5101 			wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET;  in cik_cp_compute_resume()
5103 			wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET;  in cik_cp_compute_resume()
5706 	       rdev->vram_scratch.gpu_addr >> 12);  in cik_mc_program()
7403 	WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);  in cik_irq_init()
7413 	WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);  in cik_irq_init()
7424 	WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);  in cik_irq_init()
7425 	WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);  in cik_irq_init()