Lines Matching refs:gb_tile_moden
2348 u32 reg_offset, gb_tile_moden, split_equal_to_row_size; in cik_tiling_mode_table_init() local
2374 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2380 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2386 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2392 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2398 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2404 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2409 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2415 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2421 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
2425 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2430 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2436 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2442 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2448 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2453 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2459 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2465 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2471 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2476 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2482 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2488 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2494 gb_tile_moden = 0; in cik_tiling_mode_table_init()
2497 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
2498 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2503 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2509 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2515 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2521 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2527 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2533 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2539 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2545 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2551 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2557 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2563 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2569 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2575 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2581 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2587 gb_tile_moden = 0; in cik_tiling_mode_table_init()
2590 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
2591 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2597 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2603 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2609 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2615 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2621 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2627 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2632 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2638 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2644 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
2648 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2653 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2659 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2665 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2671 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2676 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2682 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2688 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2694 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2699 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2705 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2711 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2717 gb_tile_moden = 0; in cik_tiling_mode_table_init()
2720 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
2721 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2726 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2732 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2738 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2744 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2750 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2756 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2762 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2768 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2774 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2780 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2786 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2792 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2798 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2804 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2810 gb_tile_moden = 0; in cik_tiling_mode_table_init()
2813 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
2814 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2821 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2827 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2833 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2839 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2845 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2851 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2856 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2862 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2868 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
2872 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2877 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2883 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2889 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2895 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2900 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2906 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2912 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2918 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2923 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2929 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2935 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2941 gb_tile_moden = 0; in cik_tiling_mode_table_init()
2944 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
2945 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2951 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2957 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2963 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2969 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2975 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2981 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2986 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2992 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2998 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
3002 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
3007 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3013 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
3019 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3025 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
3030 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3036 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
3042 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3048 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
3053 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3059 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
3065 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3071 gb_tile_moden = 0; in cik_tiling_mode_table_init()
3074 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
3075 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
3081 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3087 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3093 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3099 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3105 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3111 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3117 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3123 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
3129 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
3135 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3141 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3147 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3153 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3159 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3165 gb_tile_moden = 0; in cik_tiling_mode_table_init()
3168 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
3169 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
3175 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3181 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3187 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3193 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3199 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3205 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
3210 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3216 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3222 gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
3226 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
3231 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3237 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
3243 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3249 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
3254 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3260 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
3266 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3272 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
3277 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3283 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
3289 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3295 gb_tile_moden = 0; in cik_tiling_mode_table_init()
3298 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
3299 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
3304 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
3310 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
3316 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3322 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3328 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3334 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3340 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3346 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in cik_tiling_mode_table_init()
3352 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in cik_tiling_mode_table_init()
3358 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
3364 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
3370 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3376 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3382 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3388 gb_tile_moden = 0; in cik_tiling_mode_table_init()
3391 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
3392 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()