Lines Matching refs:gb_addr_config
3558 u32 gb_addr_config = RREG32(GB_ADDR_CONFIG); in cik_gpu_init() local
3580 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in cik_gpu_init()
3597 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; in cik_gpu_init()
3641 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in cik_gpu_init()
3660 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in cik_gpu_init()
3694 gb_addr_config &= ~ROW_SIZE_MASK; in cik_gpu_init()
3698 gb_addr_config |= ROW_SIZE(0); in cik_gpu_init()
3701 gb_addr_config |= ROW_SIZE(1); in cik_gpu_init()
3704 gb_addr_config |= ROW_SIZE(2); in cik_gpu_init()
3735 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; in cik_gpu_init()
3737 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; in cik_gpu_init()
3739 WREG32(GB_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3740 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3741 WREG32(DMIF_ADDR_CALC, gb_addr_config); in cik_gpu_init()
3742 WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
3743 WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
3744 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3745 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3746 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()