Lines Matching refs:WREG32
186 WREG32(CIK_DIDT_IND_INDEX, (reg)); in cik_didt_rreg()
197 WREG32(CIK_DIDT_IND_INDEX, (reg)); in cik_didt_wreg()
198 WREG32(CIK_DIDT_IND_DATA, (v)); in cik_didt_wreg()
248 WREG32(PCIE_INDEX, reg); in cik_pciep_rreg()
260 WREG32(PCIE_INDEX, reg); in cik_pciep_wreg()
262 WREG32(PCIE_DATA, v); in cik_pciep_wreg()
1856 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl); in cik_srbm_select()
1915 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); in ci_mc_load_microcode()
1919 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ci_mc_load_microcode()
1920 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in ci_mc_load_microcode()
1925 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in ci_mc_load_microcode()
1926 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); in ci_mc_load_microcode()
1928 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); in ci_mc_load_microcode()
1929 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); in ci_mc_load_microcode()
1935 WREG32(MC_SEQ_IO_DEBUG_INDEX, 5); in ci_mc_load_microcode()
1936 WREG32(MC_SEQ_IO_DEBUG_DATA, 0x00000023); in ci_mc_load_microcode()
1937 WREG32(MC_SEQ_IO_DEBUG_INDEX, 9); in ci_mc_load_microcode()
1938 WREG32(MC_SEQ_IO_DEBUG_DATA, 0x000001f0); in ci_mc_load_microcode()
1944 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); in ci_mc_load_microcode()
1946 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); in ci_mc_load_microcode()
1950 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ci_mc_load_microcode()
1951 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); in ci_mc_load_microcode()
1952 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); in ci_mc_load_microcode()
1967 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); in ci_mc_load_microcode()
2498 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2591 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2721 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2814 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2945 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
3075 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
3169 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
3299 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
3392 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
3422 WREG32(GRBM_GFX_INDEX, data); in cik_select_se_sh()
3542 WREG32(PA_SC_RASTER_CONFIG, data); in cik_setup_rb()
3666 WREG32((0x2c14 + j), 0x00000000); in cik_gpu_init()
3667 WREG32((0x2c18 + j), 0x00000000); in cik_gpu_init()
3668 WREG32((0x2c1c + j), 0x00000000); in cik_gpu_init()
3669 WREG32((0x2c20 + j), 0x00000000); in cik_gpu_init()
3670 WREG32((0x2c24 + j), 0x00000000); in cik_gpu_init()
3673 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in cik_gpu_init()
3674 WREG32(SRBM_INT_CNTL, 0x1); in cik_gpu_init()
3675 WREG32(SRBM_INT_ACK, 0x1); in cik_gpu_init()
3677 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); in cik_gpu_init()
3739 WREG32(GB_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3740 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3741 WREG32(DMIF_ADDR_CALC, gb_addr_config); in cik_gpu_init()
3742 WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
3743 WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
3744 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3745 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3746 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3763 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); in cik_gpu_init()
3771 WREG32(SX_DEBUG_1, 0x20); in cik_gpu_init()
3773 WREG32(TA_CNTL_AUX, 0x00010000); in cik_gpu_init()
3777 WREG32(SPI_CONFIG_CNTL, tmp); in cik_gpu_init()
3779 WREG32(SQ_CONFIG, 1); in cik_gpu_init()
3781 WREG32(DB_DEBUG, 0); in cik_gpu_init()
3785 WREG32(DB_DEBUG2, tmp); in cik_gpu_init()
3789 WREG32(DB_DEBUG3, tmp); in cik_gpu_init()
3793 WREG32(CB_HW_CONTROL, tmp); in cik_gpu_init()
3795 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); in cik_gpu_init()
3797 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) | in cik_gpu_init()
3802 WREG32(VGT_NUM_INSTANCES, 1); in cik_gpu_init()
3804 WREG32(CP_PERFMON_CNTL, 0); in cik_gpu_init()
3806 WREG32(SQ_CONFIG, 0); in cik_gpu_init()
3808 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | in cik_gpu_init()
3811 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | in cik_gpu_init()
3814 WREG32(VGT_GS_VERTEX_REUSE, 16); in cik_gpu_init()
3815 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in cik_gpu_init()
3819 WREG32(HDP_MISC_CNTL, tmp); in cik_gpu_init()
3822 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); in cik_gpu_init()
3824 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); in cik_gpu_init()
3825 WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER); in cik_gpu_init()
3879 WREG32(scratch, 0xCAFEDEAD); in cik_ring_test()
4204 WREG32(scratch, 0xCAFEDEAD); in cik_ib_test()
4281 WREG32(CP_ME_CNTL, 0); in cik_cp_gfx_enable()
4285 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in cik_cp_gfx_enable()
4326 WREG32(CP_PFP_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
4328 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
4329 WREG32(CP_PFP_UCODE_ADDR, le32_to_cpu(pfp_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
4335 WREG32(CP_CE_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
4337 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
4338 WREG32(CP_CE_UCODE_ADDR, le32_to_cpu(ce_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
4344 WREG32(CP_ME_RAM_WADDR, 0); in cik_cp_gfx_load_microcode()
4346 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
4347 WREG32(CP_ME_RAM_WADDR, le32_to_cpu(me_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
4348 WREG32(CP_ME_RAM_RADDR, le32_to_cpu(me_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
4354 WREG32(CP_PFP_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
4356 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
4357 WREG32(CP_PFP_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
4361 WREG32(CP_CE_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
4363 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
4364 WREG32(CP_CE_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
4368 WREG32(CP_ME_RAM_WADDR, 0); in cik_cp_gfx_load_microcode()
4370 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
4371 WREG32(CP_ME_RAM_WADDR, 0); in cik_cp_gfx_load_microcode()
4392 WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1); in cik_cp_gfx_start()
4393 WREG32(CP_ENDIAN_SWAP, 0); in cik_cp_gfx_start()
4394 WREG32(CP_DEVICE_ID, 1); in cik_cp_gfx_start()
4469 WREG32(CP_SEM_WAIT_TIMER, 0x0); in cik_cp_gfx_resume()
4471 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in cik_cp_gfx_resume()
4474 WREG32(CP_RB_WPTR_DELAY, 0); in cik_cp_gfx_resume()
4477 WREG32(CP_RB_VMID, 0); in cik_cp_gfx_resume()
4479 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in cik_cp_gfx_resume()
4489 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4492 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in cik_cp_gfx_resume()
4494 WREG32(CP_RB0_WPTR, ring->wptr); in cik_cp_gfx_resume()
4497 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); in cik_cp_gfx_resume()
4498 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in cik_cp_gfx_resume()
4501 WREG32(SCRATCH_UMSK, 0); in cik_cp_gfx_resume()
4507 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4510 WREG32(CP_RB0_BASE, rb_addr); in cik_cp_gfx_resume()
4511 WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr)); in cik_cp_gfx_resume()
4554 WREG32(CP_RB0_WPTR, ring->wptr); in cik_gfx_set_wptr()
4612 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp); in cik_compute_stop()
4615 WREG32(CP_HQD_DEQUEUE_REQUEST, 1); in cik_compute_stop()
4621 WREG32(CP_HQD_DEQUEUE_REQUEST, 0); in cik_compute_stop()
4622 WREG32(CP_HQD_PQ_RPTR, 0); in cik_compute_stop()
4623 WREG32(CP_HQD_PQ_WPTR, 0); in cik_compute_stop()
4639 WREG32(CP_MEC_CNTL, 0); in cik_cp_compute_enable()
4650 WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT)); in cik_cp_compute_enable()
4686 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4688 WREG32(CP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4689 WREG32(CP_MEC_ME1_UCODE_ADDR, le32_to_cpu(mec_hdr->header.ucode_version)); in cik_cp_compute_load_microcode()
4700 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4702 WREG32(CP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4703 WREG32(CP_MEC_ME2_UCODE_ADDR, le32_to_cpu(mec2_hdr->header.ucode_version)); in cik_cp_compute_load_microcode()
4710 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4712 WREG32(CP_MEC_ME1_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4713 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4718 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4720 WREG32(CP_MEC_ME2_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4721 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4945 WREG32(CP_CPF_DEBUG, tmp); in cik_cp_compute_resume()
4955 WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); in cik_cp_compute_resume()
4956 WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); in cik_cp_compute_resume()
4959 WREG32(CP_HPD_EOP_VMID, 0); in cik_cp_compute_resume()
4965 WREG32(CP_HPD_EOP_CONTROL, tmp); in cik_cp_compute_resume()
5025 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp); in cik_cp_compute_resume()
5034 WREG32(CP_HQD_PQ_DOORBELL_CONTROL, in cik_cp_compute_resume()
5042 WREG32(CP_HQD_DEQUEUE_REQUEST, 1); in cik_cp_compute_resume()
5048 WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request); in cik_cp_compute_resume()
5049 WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr); in cik_cp_compute_resume()
5050 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); in cik_cp_compute_resume()
5056 WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr); in cik_cp_compute_resume()
5057 WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi); in cik_cp_compute_resume()
5061 WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control); in cik_cp_compute_resume()
5067 WREG32(CP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base); in cik_cp_compute_resume()
5068 WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi); in cik_cp_compute_resume()
5086 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); in cik_cp_compute_resume()
5095 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr); in cik_cp_compute_resume()
5096 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR_HI, in cik_cp_compute_resume()
5107 WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR, in cik_cp_compute_resume()
5109 WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR_HI, in cik_cp_compute_resume()
5126 WREG32(CP_HQD_PQ_DOORBELL_CONTROL, in cik_cp_compute_resume()
5132 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); in cik_cp_compute_resume()
5137 WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid); in cik_cp_compute_resume()
5141 WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active); in cik_cp_compute_resume()
5360 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_soft_reset()
5363 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); in cik_gpu_soft_reset()
5369 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
5375 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
5425 WREG32(GRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5431 WREG32(GRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5439 WREG32(SRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5445 WREG32(SRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5471 WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP); in kv_save_regs_for_reset()
5472 WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE | in kv_save_regs_for_reset()
5481 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5482 WREG32(GMCON_PGFSM_CONFIG, 0x200010ff); in kv_restore_regs_for_reset()
5485 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5487 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5488 WREG32(GMCON_PGFSM_CONFIG, 0x300010ff); in kv_restore_regs_for_reset()
5491 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5493 WREG32(GMCON_PGFSM_WRITE, 0x210000); in kv_restore_regs_for_reset()
5494 WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff); in kv_restore_regs_for_reset()
5497 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5499 WREG32(GMCON_PGFSM_WRITE, 0x21003); in kv_restore_regs_for_reset()
5500 WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff); in kv_restore_regs_for_reset()
5503 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5505 WREG32(GMCON_PGFSM_WRITE, 0x2b00); in kv_restore_regs_for_reset()
5506 WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff); in kv_restore_regs_for_reset()
5509 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5511 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5512 WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff); in kv_restore_regs_for_reset()
5515 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5517 WREG32(GMCON_PGFSM_WRITE, 0x420000); in kv_restore_regs_for_reset()
5518 WREG32(GMCON_PGFSM_CONFIG, 0x100010ff); in kv_restore_regs_for_reset()
5521 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5523 WREG32(GMCON_PGFSM_WRITE, 0x120202); in kv_restore_regs_for_reset()
5524 WREG32(GMCON_PGFSM_CONFIG, 0x500010ff); in kv_restore_regs_for_reset()
5527 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5529 WREG32(GMCON_PGFSM_WRITE, 0x3e3e36); in kv_restore_regs_for_reset()
5530 WREG32(GMCON_PGFSM_CONFIG, 0x600010ff); in kv_restore_regs_for_reset()
5533 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5535 WREG32(GMCON_PGFSM_WRITE, 0x373f3e); in kv_restore_regs_for_reset()
5536 WREG32(GMCON_PGFSM_CONFIG, 0x700010ff); in kv_restore_regs_for_reset()
5539 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5541 WREG32(GMCON_PGFSM_WRITE, 0x3e1332); in kv_restore_regs_for_reset()
5542 WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff); in kv_restore_regs_for_reset()
5544 WREG32(GMCON_MISC3, save->gmcon_misc3); in kv_restore_regs_for_reset()
5545 WREG32(GMCON_MISC, save->gmcon_misc); in kv_restore_regs_for_reset()
5546 WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute); in kv_restore_regs_for_reset()
5564 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_pci_config_reset()
5567 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); in cik_gpu_pci_config_reset()
5572 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
5576 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
5686 WREG32((0x2c14 + j), 0x00000000); in cik_mc_program()
5687 WREG32((0x2c18 + j), 0x00000000); in cik_mc_program()
5688 WREG32((0x2c1c + j), 0x00000000); in cik_mc_program()
5689 WREG32((0x2c20 + j), 0x00000000); in cik_mc_program()
5690 WREG32((0x2c24 + j), 0x00000000); in cik_mc_program()
5692 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); in cik_mc_program()
5699 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in cik_mc_program()
5701 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in cik_mc_program()
5703 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in cik_mc_program()
5705 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, in cik_mc_program()
5709 WREG32(MC_VM_FB_LOCATION, tmp); in cik_mc_program()
5711 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in cik_mc_program()
5712 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); in cik_mc_program()
5713 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); in cik_mc_program()
5714 WREG32(MC_VM_AGP_BASE, 0); in cik_mc_program()
5715 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); in cik_mc_program()
5716 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); in cik_mc_program()
5809 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0); in cik_pcie_gart_tlb_flush()
5812 WREG32(VM_INVALIDATE_REQUEST, 0x1); in cik_pcie_gart_tlb_flush()
5828 WREG32(SH_MEM_CONFIG, sh_mem_config); in cik_pcie_init_compute_vmid()
5829 WREG32(SH_MEM_APE1_BASE, 1); in cik_pcie_init_compute_vmid()
5830 WREG32(SH_MEM_APE1_LIMIT, 0); in cik_pcie_init_compute_vmid()
5831 WREG32(SH_MEM_BASES, sh_mem_bases); in cik_pcie_init_compute_vmid()
5860 WREG32(MC_VM_MX_L1_TLB_CNTL, in cik_pcie_gart_enable()
5868 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in cik_pcie_gart_enable()
5874 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cik_pcie_gart_enable()
5875 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_enable()
5879 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in cik_pcie_gart_enable()
5880 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in cik_pcie_gart_enable()
5881 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in cik_pcie_gart_enable()
5882 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in cik_pcie_gart_enable()
5884 WREG32(VM_CONTEXT0_CNTL2, 0); in cik_pcie_gart_enable()
5885 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cik_pcie_gart_enable()
5888 WREG32(0x15D4, 0); in cik_pcie_gart_enable()
5889 WREG32(0x15D8, 0); in cik_pcie_gart_enable()
5890 WREG32(0x15DC, 0); in cik_pcie_gart_enable()
5894 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); in cik_pcie_gart_enable()
5895 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1); in cik_pcie_gart_enable()
5898 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), in cik_pcie_gart_enable()
5901 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), in cik_pcie_gart_enable()
5906 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, in cik_pcie_gart_enable()
5908 WREG32(VM_CONTEXT1_CNTL2, 4); in cik_pcie_gart_enable()
5909 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cik_pcie_gart_enable()
5927 WREG32(CHUB_CONTROL, tmp); in cik_pcie_gart_enable()
5936 WREG32(SH_MEM_CONFIG, 0); in cik_pcie_gart_enable()
5937 WREG32(SH_MEM_APE1_BASE, 1); in cik_pcie_gart_enable()
5938 WREG32(SH_MEM_APE1_LIMIT, 0); in cik_pcie_gart_enable()
5939 WREG32(SH_MEM_BASES, 0); in cik_pcie_gart_enable()
5941 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5942 WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5943 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5944 WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5981 WREG32(VM_CONTEXT0_CNTL, 0); in cik_pcie_gart_disable()
5982 WREG32(VM_CONTEXT1_CNTL, 0); in cik_pcie_gart_disable()
5984 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | in cik_pcie_gart_disable()
5987 WREG32(VM_L2_CNTL, in cik_pcie_gart_disable()
5993 WREG32(VM_L2_CNTL2, 0); in cik_pcie_gart_disable()
5994 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_disable()
6199 WREG32(CP_INT_CNTL_RING0, tmp); in cik_enable_gui_idle_interrupt()
6211 WREG32(RLC_LB_CNTL, tmp); in cik_enable_lbpw()
6247 WREG32(RLC_CNTL, rlc); in cik_update_rlc()
6260 WREG32(RLC_CNTL, data); in cik_halt_rlc()
6279 WREG32(RLC_GPR_REG2, tmp); in cik_enter_rlc_safe_mode()
6300 WREG32(RLC_GPR_REG2, tmp); in cik_exit_rlc_safe_mode()
6312 WREG32(RLC_CNTL, 0); in cik_rlc_stop()
6328 WREG32(RLC_CNTL, RLC_ENABLE); in cik_rlc_start()
6355 WREG32(RLC_CGCG_CGLS_CTRL, tmp); in cik_rlc_resume()
6363 WREG32(RLC_LB_CNTR_INIT, 0); in cik_rlc_resume()
6364 WREG32(RLC_LB_CNTR_MAX, 0x00008000); in cik_rlc_resume()
6368 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff); in cik_rlc_resume()
6369 WREG32(RLC_LB_PARAMS, 0x00600408); in cik_rlc_resume()
6370 WREG32(RLC_LB_CNTL, 0x80000004); in cik_rlc_resume()
6373 WREG32(RLC_MC_CNTL, 0); in cik_rlc_resume()
6374 WREG32(RLC_UCODE_CNTL, 0); in cik_rlc_resume()
6385 WREG32(RLC_GPM_UCODE_ADDR, 0); in cik_rlc_resume()
6387 WREG32(RLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_rlc_resume()
6388 WREG32(RLC_GPM_UCODE_ADDR, le32_to_cpu(hdr->header.ucode_version)); in cik_rlc_resume()
6410 WREG32(RLC_GPM_UCODE_ADDR, 0); in cik_rlc_resume()
6412 WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_rlc_resume()
6413 WREG32(RLC_GPM_UCODE_ADDR, 0); in cik_rlc_resume()
6420 WREG32(RLC_DRIVER_DMA_STATUS, 0); in cik_rlc_resume()
6440 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in cik_enable_cgcg()
6441 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in cik_enable_cgcg()
6443 WREG32(RLC_SERDES_WR_CTRL, tmp2); in cik_enable_cgcg()
6461 WREG32(RLC_CGCG_CGLS_CTRL, data); in cik_enable_cgcg()
6475 WREG32(CP_MEM_SLP_CNTL, data); in cik_enable_mgcg()
6483 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); in cik_enable_mgcg()
6489 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6490 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6492 WREG32(RLC_SERDES_WR_CTRL, data); in cik_enable_mgcg()
6510 WREG32(CGTS_SM_CTRL_REG, data); in cik_enable_mgcg()
6516 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); in cik_enable_mgcg()
6521 WREG32(RLC_MEM_SLP_CNTL, data); in cik_enable_mgcg()
6527 WREG32(CP_MEM_SLP_CNTL, data); in cik_enable_mgcg()
6533 WREG32(CGTS_SM_CTRL_REG, data); in cik_enable_mgcg()
6539 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6540 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6542 WREG32(RLC_SERDES_WR_CTRL, data); in cik_enable_mgcg()
6575 WREG32(mc_cg_registers[i], data); in cik_enable_mc_ls()
6592 WREG32(mc_cg_registers[i], data); in cik_enable_mc_mgcg()
6602 WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
6603 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
6608 WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
6613 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
6626 WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6631 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6636 WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6641 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6658 WREG32(UVD_CGC_CTRL, data); in cik_enable_uvd_mgcg()
6667 WREG32(UVD_CGC_CTRL, data); in cik_enable_uvd_mgcg()
6702 WREG32(HDP_HOST_PATH_CNTL, data); in cik_enable_hdp_mgcg()
6718 WREG32(HDP_MEM_POWER_LS, data); in cik_enable_hdp_ls()
6806 WREG32(RLC_PG_CNTL, data); in cik_enable_sck_slowdown_on_pu()
6820 WREG32(RLC_PG_CNTL, data); in cik_enable_sck_slowdown_on_pd()
6833 WREG32(RLC_PG_CNTL, data); in cik_enable_cp_pg()
6846 WREG32(RLC_PG_CNTL, data); in cik_enable_gds_pg()
6946 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_cgpg()
6951 WREG32(RLC_AUTO_PG_CTRL, data); in cik_enable_gfx_cgpg()
6956 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_cgpg()
6961 WREG32(RLC_AUTO_PG_CTRL, data); in cik_enable_gfx_cgpg()
7017 WREG32(RLC_PG_AO_CU_MASK, tmp); in cik_init_ao_cu_mask()
7022 WREG32(RLC_MAX_PG_CU, tmp); in cik_init_ao_cu_mask()
7036 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_static_mgpg()
7050 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_dynamic_mgpg()
7062 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); in cik_init_gfx_cgpg()
7063 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
7064 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
7065 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size); in cik_init_gfx_cgpg()
7067 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); in cik_init_gfx_cgpg()
7069 WREG32(RLC_GPM_SCRATCH_DATA, 0); in cik_init_gfx_cgpg()
7072 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); in cik_init_gfx_cgpg()
7074 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]); in cik_init_gfx_cgpg()
7080 WREG32(RLC_PG_CNTL, data); in cik_init_gfx_cgpg()
7082 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in cik_init_gfx_cgpg()
7083 WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8); in cik_init_gfx_cgpg()
7088 WREG32(CP_RB_WPTR_POLL_CNTL, data); in cik_init_gfx_cgpg()
7091 WREG32(RLC_PG_DELAY, data); in cik_init_gfx_cgpg()
7096 WREG32(RLC_PG_DELAY_2, data); in cik_init_gfx_cgpg()
7101 WREG32(RLC_AUTO_PG_CTRL, data); in cik_init_gfx_cgpg()
7264 WREG32(IH_CNTL, ih_cntl); in cik_enable_interrupts()
7265 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_enable_interrupts()
7283 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_disable_interrupts()
7284 WREG32(IH_CNTL, ih_cntl); in cik_disable_interrupts()
7286 WREG32(IH_RB_RPTR, 0); in cik_disable_interrupts()
7287 WREG32(IH_RB_WPTR, 0); in cik_disable_interrupts()
7306 WREG32(CP_INT_CNTL_RING0, tmp); in cik_disable_interrupt_state()
7309 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
7311 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
7313 WREG32(CP_ME1_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
7314 WREG32(CP_ME1_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state()
7315 WREG32(CP_ME1_PIPE2_INT_CNTL, 0); in cik_disable_interrupt_state()
7316 WREG32(CP_ME1_PIPE3_INT_CNTL, 0); in cik_disable_interrupt_state()
7317 WREG32(CP_ME2_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
7318 WREG32(CP_ME2_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state()
7319 WREG32(CP_ME2_PIPE2_INT_CNTL, 0); in cik_disable_interrupt_state()
7320 WREG32(CP_ME2_PIPE3_INT_CNTL, 0); in cik_disable_interrupt_state()
7322 WREG32(GRBM_INT_CNTL, 0); in cik_disable_interrupt_state()
7324 WREG32(SRBM_INT_CNTL, 0); in cik_disable_interrupt_state()
7326 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7327 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7329 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7330 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7333 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7334 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7338 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7339 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7342 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7343 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7346 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7347 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7351 WREG32(DAC_AUTODETECT_INT_CONTROL, 0); in cik_disable_interrupt_state()
7355 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7357 WREG32(DC_HPD2_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7359 WREG32(DC_HPD3_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7361 WREG32(DC_HPD4_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7363 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7365 WREG32(DC_HPD6_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7403 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); in cik_irq_init()
7411 WREG32(INTERRUPT_CNTL, interrupt_cntl); in cik_irq_init()
7413 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in cik_irq_init()
7424 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in cik_irq_init()
7425 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in cik_irq_init()
7427 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_irq_init()
7430 WREG32(IH_RB_RPTR, 0); in cik_irq_init()
7431 WREG32(IH_RB_WPTR, 0); in cik_irq_init()
7438 WREG32(IH_CNTL, ih_cntl); in cik_irq_init()
7600 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()
7602 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl); in cik_irq_set()
7603 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1); in cik_irq_set()
7605 WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0); in cik_irq_set()
7607 WREG32(GRBM_INT_CNTL, grbm_int_cntl); in cik_irq_set()
7609 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); in cik_irq_set()
7610 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in cik_irq_set()
7612 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); in cik_irq_set()
7613 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); in cik_irq_set()
7616 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); in cik_irq_set()
7617 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in cik_irq_set()
7621 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in cik_irq_set()
7623 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_set()
7627 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_set()
7629 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_set()
7633 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_set()
7635 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, in cik_irq_set()
7639 WREG32(DC_HPD1_INT_CONTROL, hpd1); in cik_irq_set()
7640 WREG32(DC_HPD2_INT_CONTROL, hpd2); in cik_irq_set()
7641 WREG32(DC_HPD3_INT_CONTROL, hpd3); in cik_irq_set()
7642 WREG32(DC_HPD4_INT_CONTROL, hpd4); in cik_irq_set()
7643 WREG32(DC_HPD5_INT_CONTROL, hpd5); in cik_irq_set()
7644 WREG32(DC_HPD6_INT_CONTROL, hpd6); in cik_irq_set()
7691 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, in cik_irq_ack()
7694 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_ack()
7697 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7699 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7701 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7703 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7707 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_ack()
7710 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_ack()
7713 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7715 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7717 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7719 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7724 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_ack()
7727 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, in cik_irq_ack()
7730 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7732 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7734 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7736 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7742 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_irq_ack()
7747 WREG32(DC_HPD2_INT_CONTROL, tmp); in cik_irq_ack()
7752 WREG32(DC_HPD3_INT_CONTROL, tmp); in cik_irq_ack()
7757 WREG32(DC_HPD4_INT_CONTROL, tmp); in cik_irq_ack()
7762 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_irq_ack()
7767 WREG32(DC_HPD6_INT_CONTROL, tmp); in cik_irq_ack()
7772 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_irq_ack()
7777 WREG32(DC_HPD2_INT_CONTROL, tmp); in cik_irq_ack()
7782 WREG32(DC_HPD3_INT_CONTROL, tmp); in cik_irq_ack()
7787 WREG32(DC_HPD4_INT_CONTROL, tmp); in cik_irq_ack()
7792 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_irq_ack()
7797 WREG32(DC_HPD6_INT_CONTROL, tmp); in cik_irq_ack()
7877 WREG32(IH_RB_CNTL, tmp); in cik_get_ih_wptr()
8267 WREG32(SRBM_INT_ACK, 0x1); in cik_irq_process()
8466 WREG32(IH_RB_RPTR, rptr); in cik_irq_process()
9077 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_fmt()
9127 WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset, in dce8_line_buffer_adjust()
9130 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce8_line_buffer_adjust()
9639 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_watermarks()
9640 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce8_program_watermarks()
9647 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_watermarks()
9648 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce8_program_watermarks()
9652 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask); in dce8_program_watermarks()
9703 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); in cik_get_gpu_clock_counter()