Lines Matching defs:hqd_registers
4850 struct hqd_registers struct
4852 u32 cp_mqd_base_addr;
4853 u32 cp_mqd_base_addr_hi;
4854 u32 cp_hqd_active;
4855 u32 cp_hqd_vmid;
4856 u32 cp_hqd_persistent_state;
4857 u32 cp_hqd_pipe_priority;
4858 u32 cp_hqd_queue_priority;
4859 u32 cp_hqd_quantum;
4860 u32 cp_hqd_pq_base;
4861 u32 cp_hqd_pq_base_hi;
4862 u32 cp_hqd_pq_rptr;
4863 u32 cp_hqd_pq_rptr_report_addr;
4864 u32 cp_hqd_pq_rptr_report_addr_hi;
4865 u32 cp_hqd_pq_wptr_poll_addr;
4866 u32 cp_hqd_pq_wptr_poll_addr_hi;
4867 u32 cp_hqd_pq_doorbell_control;
4868 u32 cp_hqd_pq_wptr;
4869 u32 cp_hqd_pq_control;
4870 u32 cp_hqd_ib_base_addr;
4871 u32 cp_hqd_ib_base_addr_hi;
4872 u32 cp_hqd_ib_rptr;
4873 u32 cp_hqd_ib_control;
4874 u32 cp_hqd_iq_timer;
4875 u32 cp_hqd_iq_rptr;
4876 u32 cp_hqd_dequeue_request;
4877 u32 cp_hqd_dma_offload;
4878 u32 cp_hqd_sema_cmd;
4879 u32 cp_hqd_msg_type;
4880 u32 cp_hqd_atomic0_preop_lo;
4881 u32 cp_hqd_atomic0_preop_hi;
4882 u32 cp_hqd_atomic1_preop_lo;
4883 u32 cp_hqd_atomic1_preop_hi;
4884 u32 cp_hqd_hq_scheduler0;
4885 u32 cp_hqd_hq_scheduler1;
4886 u32 cp_mqd_control;