Lines Matching defs:ci_power_info
193 struct ci_power_info { struct
194 struct ci_dpm_table dpm_table;
195 u32 voltage_control;
196 u32 mvdd_control;
197 u32 vddci_control;
198 u32 active_auto_throttle_sources;
199 struct ci_clock_registers clock_registers;
200 u16 acpi_vddc;
201 u16 acpi_vddci;
202 enum radeon_pcie_gen force_pcie_gen;
203 enum radeon_pcie_gen acpi_pcie_gen;
204 struct ci_leakage_voltage vddc_leakage;
205 struct ci_leakage_voltage vddci_leakage;
206 u16 max_vddc_in_pp_table;
207 u16 min_vddc_in_pp_table;
208 u16 max_vddci_in_pp_table;
209 u16 min_vddci_in_pp_table;
210 u32 mclk_strobe_mode_threshold;
211 u32 mclk_stutter_mode_threshold;
212 u32 mclk_edc_enable_threshold;
213 u32 mclk_edc_wr_enable_threshold;
214 struct ci_vbios_boot_state vbios_boot_state;
216 u32 sram_end;
217 u32 dpm_table_start;
218 u32 soft_regs_start;
219 u32 mc_reg_table_start;
220 u32 fan_table_start;
221 u32 arb_table_start;
223 SMU7_Discrete_DpmTable smc_state_table;
224 SMU7_Discrete_MCRegisters smc_mc_reg_table;
225 SMU7_Discrete_PmFuses smc_powertune_table;
227 struct ci_mc_reg_table mc_reg_table;
228 struct atom_voltage_table vddc_voltage_table;
229 struct atom_voltage_table vddci_voltage_table;
230 struct atom_voltage_table mvdd_voltage_table;
231 struct ci_ulv_parm ulv;
232 u32 power_containment_features;
233 const struct ci_pt_defaults *powertune_defaults;
234 u32 dte_tj_offset;
235 bool vddc_phase_shed_control;
236 struct ci_thermal_temperature_setting thermal_temp_setting;
237 struct ci_dpm_level_enable_mask dpm_level_enable_mask;
238 u32 need_update_smu7_dpm_table;
239 u32 sclk_dpm_key_disabled;
240 u32 mclk_dpm_key_disabled;
241 u32 pcie_dpm_key_disabled;
242 u32 thermal_sclk_dpm_enabled;
243 struct ci_pcie_perf_range pcie_gen_performance;
244 struct ci_pcie_perf_range pcie_lane_performance;
245 struct ci_pcie_perf_range pcie_gen_powersaving;
246 struct ci_pcie_perf_range pcie_lane_powersaving;
247 u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS];
248 u32 mclk_activity_target;
249 u32 low_sclk_interrupt_t;
250 u32 last_mclk_dpm_enable_mask;
251 u32 sys_pcie_mask;
253 bool caps_power_containment;
254 bool caps_cac;
255 bool caps_sq_ramping;
256 bool caps_db_ramping;
257 bool caps_td_ramping;
258 bool caps_tcp_ramping;
259 bool caps_fps;
260 bool caps_sclk_ds;
261 bool caps_sclk_ss_support;
262 bool caps_mclk_ss_support;
263 bool caps_uvd_dpm;
264 bool caps_vce_dpm;
265 bool caps_samu_dpm;
266 bool caps_acp_dpm;
267 bool caps_automatic_dc_transition;
268 bool caps_sclk_throttle_low_notification;
269 bool caps_dynamic_ac_timing;
270 bool caps_od_fuzzy_fan_control_support;
272 bool thermal_protection;
273 bool pcie_performance_request;
274 bool dynamic_ss;
275 bool dll_default_on;
276 bool cac_enabled;
277 bool uvd_enabled;
278 bool battery_state;
279 bool pspp_notify_required;
280 bool mem_gddr5;
281 bool enable_bapm_feature;
282 bool enable_tdc_limit_feature;
283 bool enable_pkg_pwr_tracking_feature;
284 bool use_pcie_performance_levels;
285 bool use_pcie_powersaving_levels;
286 bool uvd_power_gated;
288 struct radeon_ps current_rps;
289 struct ci_ps current_ps;
290 struct radeon_ps requested_rps;
291 struct ci_ps requested_ps;
293 bool fan_ctrl_is_in_default_mode;
294 bool fan_is_controlled_by_smc;
295 u32 t_min;
296 u32 fan_ctrl_default_mode;