200 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)  in ci_get_ps()  argument
202 	struct ci_ps *ps = rps->ps_priv;  in ci_get_ps()
787 					struct radeon_ps *rps)  in ci_apply_state_adjust_rules()  argument
789 	struct ci_ps *ps = ci_get_ps(rps);  in ci_apply_state_adjust_rules()
796 	if (rps->vce_active) {  in ci_apply_state_adjust_rules()
797 		rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;  in ci_apply_state_adjust_rules()
798 		rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;  in ci_apply_state_adjust_rules()
800 		rps->evclk = 0;  in ci_apply_state_adjust_rules()
801 		rps->ecclk = 0;  in ci_apply_state_adjust_rules()
810 	if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)  in ci_apply_state_adjust_rules()
839 	if (rps->vce_active) {  in ci_apply_state_adjust_rules()
5074 				 struct radeon_ps *rps)  in ci_update_current_ps()  argument
5076 	struct ci_ps *new_ps = ci_get_ps(rps);  in ci_update_current_ps()
5079 	pi->current_rps = *rps;  in ci_update_current_ps()
5085 				   struct radeon_ps *rps)  in ci_update_requested_ps()  argument
5087 	struct ci_ps *new_ps = ci_get_ps(rps);  in ci_update_requested_ps()
5090 	pi->requested_rps = *rps;  in ci_update_requested_ps()
5417 					  struct radeon_ps *rps,  in ci_parse_pplib_non_clock_info()  argument
5421 	rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);  in ci_parse_pplib_non_clock_info()
5422 	rps->class = le16_to_cpu(non_clock_info->usClassification);  in ci_parse_pplib_non_clock_info()
5423 	rps->class2 = le16_to_cpu(non_clock_info->usClassification2);  in ci_parse_pplib_non_clock_info()
5426 		rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);  in ci_parse_pplib_non_clock_info()
5427 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);  in ci_parse_pplib_non_clock_info()
5429 		rps->vclk = 0;  in ci_parse_pplib_non_clock_info()
5430 		rps->dclk = 0;  in ci_parse_pplib_non_clock_info()
5433 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)  in ci_parse_pplib_non_clock_info()
5434 		rdev->pm.dpm.boot_ps = rps;  in ci_parse_pplib_non_clock_info()
5435 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)  in ci_parse_pplib_non_clock_info()
5436 		rdev->pm.dpm.uvd_ps = rps;  in ci_parse_pplib_non_clock_info()
5440 				      struct radeon_ps *rps, int index,  in ci_parse_pplib_clock_info()  argument
5444 	struct ci_ps *ps = ci_get_ps(rps);  in ci_parse_pplib_clock_info()
5462 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {  in ci_parse_pplib_clock_info()
5466 	if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {  in ci_parse_pplib_clock_info()
5473 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {  in ci_parse_pplib_clock_info()
5480 	switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {  in ci_parse_pplib_clock_info()
5897 	struct radeon_ps *rps = &pi->current_rps;  in ci_dpm_debugfs_print_current_performance_level()  local
5902 	seq_printf(m, "vce    %sabled\n", rps->vce_active ? "en" : "dis");  in ci_dpm_debugfs_print_current_performance_level()
5908 			      struct radeon_ps *rps)  in ci_dpm_print_power_state()  argument
5910 	struct ci_ps *ps = ci_get_ps(rps);  in ci_dpm_print_power_state()
5914 	r600_dpm_print_class_info(rps->class, rps->class2);  in ci_dpm_print_power_state()
5915 	r600_dpm_print_cap_info(rps->caps);  in ci_dpm_print_power_state()
5916 	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);  in ci_dpm_print_power_state()
5922 	r600_dpm_print_ps_status(rdev, rps);  in ci_dpm_print_power_state()