Lines Matching refs:pi
195 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi() local
197 return pi; in ci_get_pi()
209 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_powertune_defaults() local
219 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
225 pi->powertune_defaults = &defaults_saturn_xt; in ci_initialize_powertune_defaults()
229 pi->powertune_defaults = &defaults_hawaii_xt; in ci_initialize_powertune_defaults()
233 pi->powertune_defaults = &defaults_hawaii_pro; in ci_initialize_powertune_defaults()
243 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
247 pi->dte_tj_offset = 0; in ci_initialize_powertune_defaults()
249 pi->caps_power_containment = true; in ci_initialize_powertune_defaults()
250 pi->caps_cac = false; in ci_initialize_powertune_defaults()
251 pi->caps_sq_ramping = false; in ci_initialize_powertune_defaults()
252 pi->caps_db_ramping = false; in ci_initialize_powertune_defaults()
253 pi->caps_td_ramping = false; in ci_initialize_powertune_defaults()
254 pi->caps_tcp_ramping = false; in ci_initialize_powertune_defaults()
256 if (pi->caps_power_containment) { in ci_initialize_powertune_defaults()
257 pi->caps_cac = true; in ci_initialize_powertune_defaults()
259 pi->enable_bapm_feature = false; in ci_initialize_powertune_defaults()
261 pi->enable_bapm_feature = true; in ci_initialize_powertune_defaults()
262 pi->enable_tdc_limit_feature = true; in ci_initialize_powertune_defaults()
263 pi->enable_pkg_pwr_tracking_feature = true; in ci_initialize_powertune_defaults()
274 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_vid_sidd() local
275 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_populate_bapm_vddc_vid_sidd()
276 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_populate_bapm_vddc_vid_sidd()
277 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; in ci_populate_bapm_vddc_vid_sidd()
303 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_vddc_vid() local
304 u8 *vid = pi->smc_powertune_table.VddCVid; in ci_populate_vddc_vid()
307 if (pi->vddc_voltage_table.count > 8) in ci_populate_vddc_vid()
310 for (i = 0; i < pi->vddc_voltage_table.count; i++) in ci_populate_vddc_vid()
311 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); in ci_populate_vddc_vid()
318 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_svi_load_line() local
319 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_svi_load_line()
321 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; in ci_populate_svi_load_line()
322 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; in ci_populate_svi_load_line()
323 pi->smc_powertune_table.SviLoadLineTrimVddC = 3; in ci_populate_svi_load_line()
324 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; in ci_populate_svi_load_line()
331 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_tdc_limit() local
332 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_tdc_limit()
336 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); in ci_populate_tdc_limit()
337 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = in ci_populate_tdc_limit()
339 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; in ci_populate_tdc_limit()
346 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_dw8() local
347 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_dw8()
354 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, in ci_populate_dw8()
355 pi->sram_end); in ci_populate_dw8()
359 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; in ci_populate_dw8()
366 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_fuzzy_fan() local
373 pi->smc_powertune_table.FuzzyFan_PwmSetDelta = in ci_populate_fuzzy_fan()
381 struct ci_power_info *pi = ci_get_pi(rdev); in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc() local
382 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
383 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
405 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
406 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
413 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_base_leakage_sidd() local
414 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd; in ci_populate_bapm_vddc_base_leakage_sidd()
415 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd; in ci_populate_bapm_vddc_base_leakage_sidd()
422 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
423 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
430 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_parameters_in_dpm_table() local
431 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_bapm_parameters_in_dpm_table()
432 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table()
443 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
445 (u8)(pi->thermal_temp_setting.temperature_high / 1000); in ci_populate_bapm_parameters_in_dpm_table()
478 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_pm_base() local
482 if (pi->caps_power_containment) { in ci_populate_pm_base()
486 &pm_fuse_table_offset, pi->sram_end); in ci_populate_pm_base()
514 (u8 *)&pi->smc_powertune_table, in ci_populate_pm_base()
515 sizeof(SMU7_Discrete_PmFuses), pi->sram_end); in ci_populate_pm_base()
525 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_enable_didt() local
528 if (pi->caps_sq_ramping) { in ci_do_enable_didt()
537 if (pi->caps_db_ramping) { in ci_do_enable_didt()
546 if (pi->caps_td_ramping) { in ci_do_enable_didt()
555 if (pi->caps_tcp_ramping) { in ci_do_enable_didt()
615 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_didt() local
618 if (pi->caps_sq_ramping || pi->caps_db_ramping || in ci_enable_didt()
619 pi->caps_td_ramping || pi->caps_tcp_ramping) { in ci_enable_didt()
640 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_power_containment() local
645 pi->power_containment_features = 0; in ci_enable_power_containment()
646 if (pi->caps_power_containment) { in ci_enable_power_containment()
647 if (pi->enable_bapm_feature) { in ci_enable_power_containment()
652 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; in ci_enable_power_containment()
655 if (pi->enable_tdc_limit_feature) { in ci_enable_power_containment()
660 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; in ci_enable_power_containment()
663 if (pi->enable_pkg_pwr_tracking_feature) { in ci_enable_power_containment()
673 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; in ci_enable_power_containment()
680 if (pi->caps_power_containment && pi->power_containment_features) { in ci_enable_power_containment()
681 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) in ci_enable_power_containment()
684 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) in ci_enable_power_containment()
687 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) in ci_enable_power_containment()
689 pi->power_containment_features = 0; in ci_enable_power_containment()
698 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_smc_cac() local
702 if (pi->caps_cac) { in ci_enable_smc_cac()
707 pi->cac_enabled = false; in ci_enable_smc_cac()
709 pi->cac_enabled = true; in ci_enable_smc_cac()
711 } else if (pi->cac_enabled) { in ci_enable_smc_cac()
713 pi->cac_enabled = false; in ci_enable_smc_cac()
723 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_thermal_based_sclk_dpm() local
726 if (pi->thermal_sclk_dpm_enabled) { in ci_enable_thermal_based_sclk_dpm()
741 struct ci_power_info *pi = ci_get_pi(rdev); in ci_power_control_set_level() local
749 if (pi->caps_power_containment) { in ci_power_control_set_level()
763 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_powergate_uvd() local
765 if (pi->uvd_power_gated == gate) in ci_dpm_powergate_uvd()
768 pi->uvd_power_gated = gate; in ci_dpm_powergate_uvd()
775 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_vblank_too_short() local
777 u32 switch_limit = pi->mem_gddr5 ? 450 : 300; in ci_dpm_vblank_too_short()
790 struct ci_power_info *pi = ci_get_pi(rdev); in ci_apply_state_adjust_rules() local
811 pi->battery_state = true; in ci_apply_state_adjust_rules()
813 pi->battery_state = false; in ci_apply_state_adjust_rules()
928 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_static_mode() local
931 if (pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_static_mode()
933 pi->fan_ctrl_default_mode = tmp; in ci_fan_ctrl_set_static_mode()
935 pi->t_min = tmp; in ci_fan_ctrl_set_static_mode()
936 pi->fan_ctrl_is_in_default_mode = false; in ci_fan_ctrl_set_static_mode()
950 struct ci_power_info *pi = ci_get_pi(rdev); in ci_thermal_setup_fan_table() local
959 if (!pi->fan_table_start) { in ci_thermal_setup_fan_table()
1012 pi->fan_table_start, in ci_thermal_setup_fan_table()
1015 pi->sram_end); in ci_thermal_setup_fan_table()
1027 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_start_smc_fan_control() local
1030 if (pi->caps_od_fuzzy_fan_control_support) { in ci_fan_ctrl_start_smc_fan_control()
1049 pi->fan_is_controlled_by_smc = true; in ci_fan_ctrl_start_smc_fan_control()
1056 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_stop_smc_fan_control() local
1060 pi->fan_is_controlled_by_smc = false; in ci_fan_ctrl_stop_smc_fan_control()
1097 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_fan_speed_percent() local
1102 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_set_fan_speed_percent()
1142 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_get_mode() local
1145 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_get_mode()
1206 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_default_mode() local
1209 if (!pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_default_mode()
1211 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode); in ci_fan_ctrl_set_default_mode()
1215 tmp |= TMIN(pi->t_min); in ci_fan_ctrl_set_default_mode()
1217 pi->fan_ctrl_is_in_default_mode = true; in ci_fan_ctrl_set_default_mode()
1275 struct ci_power_info *pi = ci_get_pi(rdev);
1278 pi->soft_regs_start + reg_offset,
1279 value, pi->sram_end);
1286 struct ci_power_info *pi = ci_get_pi(rdev); in ci_write_smc_soft_register() local
1289 pi->soft_regs_start + reg_offset, in ci_write_smc_soft_register()
1290 value, pi->sram_end); in ci_write_smc_soft_register()
1295 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_fps_limits() local
1296 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits()
1298 if (pi->caps_fps) { in ci_init_fps_limits()
1311 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_sclk_t() local
1315 if (pi->caps_sclk_throttle_low_notification) { in ci_update_sclk_t()
1316 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in ci_update_sclk_t()
1319 pi->dpm_table_start + in ci_update_sclk_t()
1322 sizeof(u32), pi->sram_end); in ci_update_sclk_t()
1331 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_leakage_voltages() local
1336 pi->vddc_leakage.count = 0; in ci_get_leakage_voltages()
1337 pi->vddci_leakage.count = 0; in ci_get_leakage_voltages()
1345 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1346 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1347 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1357 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1358 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1359 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1362 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; in ci_get_leakage_voltages()
1363 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1364 pi->vddci_leakage.count++; in ci_get_leakage_voltages()
1373 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_dpm_event_sources() local
1408 if (pi->thermal_protection) in ci_set_dpm_event_sources()
1424 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_auto_throttle_source() local
1427 if (!(pi->active_auto_throttle_sources & (1 << source))) { in ci_enable_auto_throttle_source()
1428 pi->active_auto_throttle_sources |= 1 << source; in ci_enable_auto_throttle_source()
1429 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1432 if (pi->active_auto_throttle_sources & (1 << source)) { in ci_enable_auto_throttle_source()
1433 pi->active_auto_throttle_sources &= ~(1 << source); in ci_enable_auto_throttle_source()
1434 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1447 struct ci_power_info *pi = ci_get_pi(rdev); in ci_unfreeze_sclk_mclk_dpm() local
1450 if (!pi->need_update_smu7_dpm_table) in ci_unfreeze_sclk_mclk_dpm()
1453 if ((!pi->sclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1454 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_unfreeze_sclk_mclk_dpm()
1460 if ((!pi->mclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1461 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_unfreeze_sclk_mclk_dpm()
1467 pi->need_update_smu7_dpm_table = 0; in ci_unfreeze_sclk_mclk_dpm()
1473 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_sclk_mclk_dpm() local
1477 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1483 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1501 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1507 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1519 struct ci_power_info *pi = ci_get_pi(rdev); in ci_start_dpm() local
1544 if (!pi->pcie_dpm_key_disabled) { in ci_start_dpm()
1555 struct ci_power_info *pi = ci_get_pi(rdev); in ci_freeze_sclk_mclk_dpm() local
1558 if (!pi->need_update_smu7_dpm_table) in ci_freeze_sclk_mclk_dpm()
1561 if ((!pi->sclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1562 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_freeze_sclk_mclk_dpm()
1568 if ((!pi->mclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1569 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_freeze_sclk_mclk_dpm()
1580 struct ci_power_info *pi = ci_get_pi(rdev); in ci_stop_dpm() local
1593 if (!pi->pcie_dpm_key_disabled) { in ci_stop_dpm()
1625 struct ci_power_info *pi = ci_get_pi(rdev);
1637 if (pi->caps_automatic_dc_transition) {
1670 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_sclk() local
1672 if (!pi->sclk_dpm_key_disabled) { in ci_dpm_force_state_sclk()
1684 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_mclk() local
1686 if (!pi->mclk_dpm_key_disabled) { in ci_dpm_force_state_mclk()
1698 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_pcie() local
1700 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_state_pcie()
1712 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_power_limit() local
1714 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { in ci_set_power_limit()
1788 struct ci_power_info *pi = ci_get_pi(rdev); in ci_process_firmware_header() local
1795 &tmp, pi->sram_end); in ci_process_firmware_header()
1799 pi->dpm_table_start = tmp; in ci_process_firmware_header()
1804 &tmp, pi->sram_end); in ci_process_firmware_header()
1808 pi->soft_regs_start = tmp; in ci_process_firmware_header()
1813 &tmp, pi->sram_end); in ci_process_firmware_header()
1817 pi->mc_reg_table_start = tmp; in ci_process_firmware_header()
1822 &tmp, pi->sram_end); in ci_process_firmware_header()
1826 pi->fan_table_start = tmp; in ci_process_firmware_header()
1831 &tmp, pi->sram_end); in ci_process_firmware_header()
1835 pi->arb_table_start = tmp; in ci_process_firmware_header()
1842 struct ci_power_info *pi = ci_get_pi(rdev); in ci_read_clock_registers() local
1844 pi->clock_registers.cg_spll_func_cntl = in ci_read_clock_registers()
1846 pi->clock_registers.cg_spll_func_cntl_2 = in ci_read_clock_registers()
1848 pi->clock_registers.cg_spll_func_cntl_3 = in ci_read_clock_registers()
1850 pi->clock_registers.cg_spll_func_cntl_4 = in ci_read_clock_registers()
1852 pi->clock_registers.cg_spll_spread_spectrum = in ci_read_clock_registers()
1854 pi->clock_registers.cg_spll_spread_spectrum_2 = in ci_read_clock_registers()
1856 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); in ci_read_clock_registers()
1857 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); in ci_read_clock_registers()
1858 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); in ci_read_clock_registers()
1859 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ci_read_clock_registers()
1860 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); in ci_read_clock_registers()
1861 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in ci_read_clock_registers()
1862 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); in ci_read_clock_registers()
1863 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in ci_read_clock_registers()
1864 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); in ci_read_clock_registers()
1869 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_sclk_t() local
1871 pi->low_sclk_interrupt_t = 0; in ci_init_sclk_t()
1935 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ds_master_switch() local
1938 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
1946 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
1991 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_spread_spectrum() local
1995 if (pi->caps_sclk_ss_support) { in ci_enable_spread_spectrum()
2065 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_firmware() local
2077 ret = ci_load_smc_ucode(rdev, pi->sram_end); in ci_upload_firmware()
2106 struct ci_power_info *pi = ci_get_pi(rdev); in ci_construct_voltage_tables() local
2109 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2112 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2115 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2118 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2123 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) in ci_construct_voltage_tables()
2125 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2127 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2130 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2133 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2136 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2141 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) in ci_construct_voltage_tables()
2143 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2145 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2148 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2151 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2154 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2159 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) in ci_construct_voltage_tables()
2161 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2191 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddc_table() local
2194 table->VddcLevelCount = pi->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
2197 &pi->vddc_voltage_table.entries[count], in ci_populate_smc_vddc_table()
2200 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddc_table()
2202 pi->vddc_voltage_table.entries[count].smio_low; in ci_populate_smc_vddc_table()
2215 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddci_table() local
2217 table->VddciLevelCount = pi->vddci_voltage_table.count; in ci_populate_smc_vddci_table()
2220 &pi->vddci_voltage_table.entries[count], in ci_populate_smc_vddci_table()
2223 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddci_table()
2225 pi->vddci_voltage_table.entries[count].smio_low; in ci_populate_smc_vddci_table()
2237 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_mvdd_table() local
2240 table->MvddLevelCount = pi->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
2243 &pi->mvdd_voltage_table.entries[count], in ci_populate_smc_mvdd_table()
2246 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_mvdd_table()
2248 pi->mvdd_voltage_table.entries[count].smio_low; in ci_populate_smc_mvdd_table()
2280 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mvdd_value() local
2283 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_mvdd_value()
2286 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; in ci_populate_mvdd_value()
2385 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_arb_table_index() local
2389 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2390 &tmp, pi->sram_end); in ci_init_arb_table_index()
2397 return ci_write_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2398 tmp, pi->sram_end); in ci_init_arb_table_index()
2518 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_program_memory_timing_parameters() local
2525 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2526 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2528 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
2529 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
2538 pi->arb_table_start, in ci_do_program_memory_timing_parameters()
2541 pi->sram_end); in ci_do_program_memory_timing_parameters()
2548 struct ci_power_info *pi = ci_get_pi(rdev); in ci_program_memory_timing_parameters() local
2550 if (pi->need_update_smu7_dpm_table == 0) in ci_program_memory_timing_parameters()
2560 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_initial_state() local
2566 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state()
2574 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state()
2599 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_link_level() local
2600 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_smc_link_level()
2613 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
2614 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()
2764 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_mclk_params() local
2765 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_calculate_mclk_params()
2766 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_calculate_mclk_params()
2767 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; in ci_calculate_mclk_params()
2768 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; in ci_calculate_mclk_params()
2769 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; in ci_calculate_mclk_params()
2770 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; in ci_calculate_mclk_params()
2771 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; in ci_calculate_mclk_params()
2772 u32 mpll_ss1 = pi->clock_registers.mpll_ss1; in ci_calculate_mclk_params()
2773 u32 mpll_ss2 = pi->clock_registers.mpll_ss2; in ci_calculate_mclk_params()
2791 if (pi->mem_gddr5) { in ci_calculate_mclk_params()
2797 if (pi->caps_mclk_ss_support) { in ci_calculate_mclk_params()
2849 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_memory_level() local
2879 if (pi->vddc_phase_shed_control) in ci_populate_single_memory_level()
2889 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; in ci_populate_single_memory_level()
2899 if (pi->mclk_stutter_mode_threshold && in ci_populate_single_memory_level()
2900 (memory_clock <= pi->mclk_stutter_mode_threshold) && in ci_populate_single_memory_level()
2901 (pi->uvd_enabled == false) && in ci_populate_single_memory_level()
2906 if (pi->mclk_strobe_mode_threshold && in ci_populate_single_memory_level()
2907 (memory_clock <= pi->mclk_strobe_mode_threshold)) in ci_populate_single_memory_level()
2910 if (pi->mem_gddr5) { in ci_populate_single_memory_level()
2913 if (pi->mclk_edc_enable_threshold && in ci_populate_single_memory_level()
2914 (memory_clock > pi->mclk_edc_enable_threshold)) in ci_populate_single_memory_level()
2917 if (pi->mclk_edc_wr_enable_threshold && in ci_populate_single_memory_level()
2918 (memory_clock > pi->mclk_edc_wr_enable_threshold)) in ci_populate_single_memory_level()
2928 dll_state_on = pi->dll_default_on; in ci_populate_single_memory_level()
2962 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_acpi_level() local
2965 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; in ci_populate_smc_acpi_level()
2966 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; in ci_populate_smc_acpi_level()
2967 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_populate_smc_acpi_level()
2968 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_populate_smc_acpi_level()
2973 if (pi->acpi_vddc) in ci_populate_smc_acpi_level()
2974 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2976 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2978 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
3000 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_populate_smc_acpi_level()
3001 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_populate_smc_acpi_level()
3002 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_populate_smc_acpi_level()
3003 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_populate_smc_acpi_level()
3022 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_smc_acpi_level()
3023 if (pi->acpi_vddci) in ci_populate_smc_acpi_level()
3025 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3028 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3045 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); in ci_populate_smc_acpi_level()
3047 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); in ci_populate_smc_acpi_level()
3049 cpu_to_be32(pi->clock_registers.mpll_func_cntl); in ci_populate_smc_acpi_level()
3051 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); in ci_populate_smc_acpi_level()
3053 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); in ci_populate_smc_acpi_level()
3054 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); in ci_populate_smc_acpi_level()
3055 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); in ci_populate_smc_acpi_level()
3063 cpu_to_be16((u16)pi->mclk_activity_target); in ci_populate_smc_acpi_level()
3077 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ulv() local
3078 struct ci_ulv_parm *ulv = &pi->ulv; in ci_enable_ulv()
3095 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_ulv_level() local
3102 pi->ulv.supported = false; in ci_populate_ulv_level()
3106 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_populate_ulv_level()
3120 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_ulv_level()
3133 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_sclk_params() local
3135 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_calculate_sclk_params()
3136 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_calculate_sclk_params()
3137 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_calculate_sclk_params()
3138 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_calculate_sclk_params()
3157 if (pi->caps_sclk_ss_support) { in ci_calculate_sclk_params()
3190 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_graphic_level() local
3208 if (pi->vddc_phase_shed_control) in ci_populate_single_graphic_level()
3224 if (pi->caps_sclk_ds) in ci_populate_single_graphic_level()
3248 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_graphic_levels() local
3249 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_graphic_levels()
3250 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_graphic_levels()
3254 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
3262 (u16)pi->activity_target[i], in ci_populate_all_graphic_levels()
3263 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3267 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3269 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
3272 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
3274 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3275 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()
3280 pi->sram_end); in ci_populate_all_graphic_levels()
3295 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_memory_levels() local
3296 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_memory_levels()
3297 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_memory_levels()
3301 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
3311 &pi->smc_state_table.MemoryLevel[i]); in ci_populate_all_memory_levels()
3316 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
3320 pi->smc_state_table.MemoryLevel[1].MinVddc = in ci_populate_all_memory_levels()
3321 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3322 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = in ci_populate_all_memory_levels()
3323 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; in ci_populate_all_memory_levels()
3326 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); in ci_populate_all_memory_levels()
3328 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3329 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_populate_all_memory_levels()
3332 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3337 pi->sram_end); in ci_populate_all_memory_levels()
3365 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_pcie_tables() local
3367 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) in ci_setup_default_pcie_tables()
3370 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3371 pi->pcie_gen_powersaving = pi->pcie_gen_performance; in ci_setup_default_pcie_tables()
3372 pi->pcie_lane_powersaving = pi->pcie_lane_performance; in ci_setup_default_pcie_tables()
3373 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3374 pi->pcie_gen_performance = pi->pcie_gen_powersaving; in ci_setup_default_pcie_tables()
3375 pi->pcie_lane_performance = pi->pcie_lane_powersaving; in ci_setup_default_pcie_tables()
3379 &pi->dpm_table.pcie_speed_table, in ci_setup_default_pcie_tables()
3383 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3384 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3385 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3387 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3388 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3389 pi->pcie_lane_powersaving.min); in ci_setup_default_pcie_tables()
3390 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, in ci_setup_default_pcie_tables()
3391 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3392 pi->pcie_lane_performance.min); in ci_setup_default_pcie_tables()
3393 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, in ci_setup_default_pcie_tables()
3394 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3395 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3396 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, in ci_setup_default_pcie_tables()
3397 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3398 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3399 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, in ci_setup_default_pcie_tables()
3400 pi->pcie_gen_powersaving.max, in ci_setup_default_pcie_tables()
3401 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3402 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, in ci_setup_default_pcie_tables()
3403 pi->pcie_gen_performance.max, in ci_setup_default_pcie_tables()
3404 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3406 pi->dpm_table.pcie_speed_table.count = 6; in ci_setup_default_pcie_tables()
3413 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_dpm_tables() local
3431 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); in ci_setup_default_dpm_tables()
3434 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3437 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
3440 &pi->dpm_table.vddc_table, in ci_setup_default_dpm_tables()
3443 &pi->dpm_table.vddci_table, in ci_setup_default_dpm_tables()
3446 &pi->dpm_table.mvdd_table, in ci_setup_default_dpm_tables()
3449 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3452 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
3454 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = in ci_setup_default_dpm_tables()
3456 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = in ci_setup_default_dpm_tables()
3458 pi->dpm_table.sclk_table.count++; in ci_setup_default_dpm_tables()
3462 pi->dpm_table.mclk_table.count = 0; in ci_setup_default_dpm_tables()
3465 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != in ci_setup_default_dpm_tables()
3467 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = in ci_setup_default_dpm_tables()
3469 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = in ci_setup_default_dpm_tables()
3471 pi->dpm_table.mclk_table.count++; in ci_setup_default_dpm_tables()
3476 pi->dpm_table.vddc_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3478 pi->dpm_table.vddc_table.dpm_levels[i].param1 = in ci_setup_default_dpm_tables()
3480 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3482 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()
3487 pi->dpm_table.vddci_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3489 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3491 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3497 pi->dpm_table.mvdd_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3499 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3501 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3527 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_smc_table() local
3528 struct ci_ulv_parm *ulv = &pi->ulv; in ci_init_smc_table()
3530 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_smc_table()
3537 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) in ci_init_smc_table()
3548 if (pi->mem_gddr5) in ci_init_smc_table()
3552 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); in ci_init_smc_table()
3599 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, in ci_init_smc_table()
3600 pi->vbios_boot_state.sclk_bootup_value, in ci_init_smc_table()
3601 (u32 *)&pi->smc_state_table.GraphicsBootLevel); in ci_init_smc_table()
3603 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, in ci_init_smc_table()
3604 pi->vbios_boot_state.mclk_bootup_value, in ci_init_smc_table()
3605 (u32 *)&pi->smc_state_table.MemoryBootLevel); in ci_init_smc_table()
3607 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; in ci_init_smc_table()
3608 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; in ci_init_smc_table()
3609 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; in ci_init_smc_table()
3626 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * in ci_init_smc_table()
3628 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * in ci_init_smc_table()
3636 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; in ci_init_smc_table()
3638 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) in ci_init_smc_table()
3662 pi->dpm_table_start + in ci_init_smc_table()
3666 pi->sram_end); in ci_init_smc_table()
3692 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_pcie_dpm_states() local
3693 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; in ci_trim_pcie_dpm_states()
3723 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_dpm_states() local
3735 &pi->dpm_table.sclk_table, in ci_trim_dpm_states()
3740 &pi->dpm_table.mclk_table, in ci_trim_dpm_states()
3787 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_dpm_level_enable_mask() local
3792 if (!pi->sclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3793 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3796 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3802 if (!pi->mclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3803 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3806 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3812 if (!pi->pcie_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3813 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3816 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3828 struct ci_power_info *pi = ci_get_pi(rdev); in ci_find_dpm_states_clocks_in_dpm_table() local
3830 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3832 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3836 pi->need_update_smu7_dpm_table = 0; in ci_find_dpm_states_clocks_in_dpm_table()
3844 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3848 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3857 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3861 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3867 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_and_upload_sclk_mclk_dpm_levels() local
3871 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3874 if (!pi->need_update_smu7_dpm_table) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3877 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3880 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3883 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3889 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3900 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_uvd_dpm() local
3910 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()
3914 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; in ci_enable_uvd_dpm()
3916 if (!pi->caps_uvd_dpm) in ci_enable_uvd_dpm()
3923 pi->dpm_level_enable_mask.uvd_dpm_enable_mask); in ci_enable_uvd_dpm()
3925 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3926 pi->uvd_enabled = true; in ci_enable_uvd_dpm()
3927 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_enable_uvd_dpm()
3930 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3933 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3934 pi->uvd_enabled = false; in ci_enable_uvd_dpm()
3935 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; in ci_enable_uvd_dpm()
3938 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3949 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_vce_dpm() local
3959 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; in ci_enable_vce_dpm()
3962 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; in ci_enable_vce_dpm()
3964 if (!pi->caps_vce_dpm) in ci_enable_vce_dpm()
3971 pi->dpm_level_enable_mask.vce_dpm_enable_mask); in ci_enable_vce_dpm()
3982 struct ci_power_info *pi = ci_get_pi(rdev);
3992 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3995 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3997 if (!pi->caps_samu_dpm)
4004 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4013 struct ci_power_info *pi = ci_get_pi(rdev);
4023 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4026 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4028 if (!pi->caps_acp_dpm)
4035 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4046 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_uvd_dpm() local
4050 if (pi->caps_uvd_dpm || in ci_update_uvd_dpm()
4052 pi->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_dpm()
4054 pi->smc_state_table.UvdBootLevel = in ci_update_uvd_dpm()
4059 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); in ci_update_uvd_dpm()
4085 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_vce_dpm() local
4094 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); in ci_update_vce_dpm()
4097 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); in ci_update_vce_dpm()
4119 struct ci_power_info *pi = ci_get_pi(rdev);
4123 pi->smc_state_table.AcpBootLevel = 0;
4127 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4138 struct ci_power_info *pi = ci_get_pi(rdev); in ci_generate_dpm_level_enable_mask() local
4145 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4146 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); in ci_generate_dpm_level_enable_mask()
4147 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4148 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); in ci_generate_dpm_level_enable_mask()
4149 pi->last_mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4150 pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_generate_dpm_level_enable_mask()
4151 if (pi->uvd_enabled) { in ci_generate_dpm_level_enable_mask()
4152 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) in ci_generate_dpm_level_enable_mask()
4153 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_generate_dpm_level_enable_mask()
4155 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4156 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); in ci_generate_dpm_level_enable_mask()
4176 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_performance_level() local
4181 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4182 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4184 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; in ci_dpm_force_performance_level()
4200 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4201 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4203 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4219 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4220 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4222 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4239 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4240 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4242 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4254 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4255 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4257 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4269 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4270 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4272 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_dpm_force_performance_level()
4285 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_performance_level()
4306 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_mc_special_registers() local
4332 if (!pi->mem_gddr5) in ci_set_mc_special_registers()
4339 if (!pi->mem_gddr5) { in ci_set_mc_special_registers()
4593 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_mc_reg_table() local
4595 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; in ci_initialize_mc_reg_table()
4653 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mc_reg_addresses() local
4656 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { in ci_populate_mc_reg_addresses()
4657 if (pi->mc_reg_table.valid_flag & (1 << j)) { in ci_populate_mc_reg_addresses()
4660 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); in ci_populate_mc_reg_addresses()
4661 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); in ci_populate_mc_reg_addresses()
4689 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_entry_to_smc() local
4692 for(i = 0; i < pi->mc_reg_table.num_entries; i++) { in ci_convert_mc_reg_table_entry_to_smc()
4693 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in ci_convert_mc_reg_table_entry_to_smc()
4697 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) in ci_convert_mc_reg_table_entry_to_smc()
4700 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], in ci_convert_mc_reg_table_entry_to_smc()
4701 mc_reg_table_data, pi->mc_reg_table.last, in ci_convert_mc_reg_table_entry_to_smc()
4702 pi->mc_reg_table.valid_flag); in ci_convert_mc_reg_table_entry_to_smc()
4708 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_to_smc() local
4711 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) in ci_convert_mc_reg_table_to_smc()
4713 pi->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
4719 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_initial_mc_reg_table() local
4722 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_populate_initial_mc_reg_table()
4724 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4727 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4730 pi->mc_reg_table_start, in ci_populate_initial_mc_reg_table()
4731 (u8 *)&pi->smc_mc_reg_table, in ci_populate_initial_mc_reg_table()
4733 pi->sram_end); in ci_populate_initial_mc_reg_table()
4738 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_and_upload_mc_reg_table() local
4740 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()
4743 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_update_and_upload_mc_reg_table()
4745 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_update_and_upload_mc_reg_table()
4748 pi->mc_reg_table_start + in ci_update_and_upload_mc_reg_table()
4750 (u8 *)&pi->smc_mc_reg_table.data[0], in ci_update_and_upload_mc_reg_table()
4752 pi->dpm_table.mclk_table.count, in ci_update_and_upload_mc_reg_table()
4753 pi->sram_end); in ci_update_and_upload_mc_reg_table()
4820 struct ci_power_info *pi = ci_get_pi(rdev); in ci_request_link_speed_change_before_state_change() local
4825 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) in ci_request_link_speed_change_before_state_change()
4828 current_link_speed = pi->force_pcie_gen; in ci_request_link_speed_change_before_state_change()
4830 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_request_link_speed_change_before_state_change()
4831 pi->pspp_notify_required = false; in ci_request_link_speed_change_before_state_change()
4838 pi->force_pcie_gen = RADEON_PCIE_GEN2; in ci_request_link_speed_change_before_state_change()
4846 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev); in ci_request_link_speed_change_before_state_change()
4851 pi->pspp_notify_required = true; in ci_request_link_speed_change_before_state_change()
4859 struct ci_power_info *pi = ci_get_pi(rdev); in ci_notify_link_speed_change_after_state_change() local
4864 if (pi->pspp_notify_required) { in ci_notify_link_speed_change_after_state_change()
4884 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_private_data_variables_based_on_pptable() local
4905 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4906 pi->max_vddc_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4909 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4910 pi->max_vddci_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4927 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddc_leakage() local
4928 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; in ci_patch_with_vddc_leakage()
4941 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddci_leakage() local
4942 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; in ci_patch_with_vddci_leakage()
5060 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_memory_type() local
5067 pi->mem_gddr5 = true; in ci_get_memory_type()
5069 pi->mem_gddr5 = false; in ci_get_memory_type()
5077 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_current_ps() local
5079 pi->current_rps = *rps; in ci_update_current_ps()
5080 pi->current_ps = *new_ps; in ci_update_current_ps()
5081 pi->current_rps.ps_priv = &pi->current_ps; in ci_update_current_ps()
5088 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_requested_ps() local
5090 pi->requested_rps = *rps; in ci_update_requested_ps()
5091 pi->requested_ps = *new_ps; in ci_update_requested_ps()
5092 pi->requested_rps.ps_priv = &pi->requested_ps; in ci_update_requested_ps()
5097 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_pre_set_power_state() local
5103 ci_apply_state_adjust_rules(rdev, &pi->requested_rps); in ci_dpm_pre_set_power_state()
5110 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_post_set_power_state() local
5111 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_post_set_power_state()
5132 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_enable() local
5138 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_dpm_enable()
5146 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5149 pi->caps_dynamic_ac_timing = false; in ci_dpm_enable()
5151 if (pi->dynamic_ss) in ci_dpm_enable()
5153 if (pi->thermal_protection) in ci_dpm_enable()
5183 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5287 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_disable() local
5297 if (pi->thermal_protection) in ci_dpm_disable()
5318 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_set_power_state() local
5319 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_set_power_state()
5320 struct radeon_ps *old_ps = &pi->current_rps; in ci_dpm_set_power_state()
5324 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5353 if (pi->caps_dynamic_ac_timing) { in ci_dpm_set_power_state()
5375 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5443 struct ci_power_info *pi = ci_get_pi(rdev); in ci_parse_pplib_clock_info() local
5455 pi->sys_pcie_mask, in ci_parse_pplib_clock_info()
5456 pi->vbios_boot_state.pcie_gen_bootup_value, in ci_parse_pplib_clock_info()
5459 pi->vbios_boot_state.pcie_lane_bootup_value, in ci_parse_pplib_clock_info()
5463 pi->acpi_pcie_gen = pl->pcie_gen; in ci_parse_pplib_clock_info()
5467 pi->ulv.supported = true; in ci_parse_pplib_clock_info()
5468 pi->ulv.pl = *pl; in ci_parse_pplib_clock_info()
5469 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; in ci_parse_pplib_clock_info()
5474 pl->mclk = pi->vbios_boot_state.mclk_bootup_value; in ci_parse_pplib_clock_info()
5475 pl->sclk = pi->vbios_boot_state.sclk_bootup_value; in ci_parse_pplib_clock_info()
5476 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; in ci_parse_pplib_clock_info()
5477 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; in ci_parse_pplib_clock_info()
5482 pi->use_pcie_powersaving_levels = true; in ci_parse_pplib_clock_info()
5483 if (pi->pcie_gen_powersaving.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5484 pi->pcie_gen_powersaving.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5485 if (pi->pcie_gen_powersaving.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5486 pi->pcie_gen_powersaving.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5487 if (pi->pcie_lane_powersaving.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5488 pi->pcie_lane_powersaving.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5489 if (pi->pcie_lane_powersaving.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5490 pi->pcie_lane_powersaving.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5493 pi->use_pcie_performance_levels = true; in ci_parse_pplib_clock_info()
5494 if (pi->pcie_gen_performance.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5495 pi->pcie_gen_performance.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5496 if (pi->pcie_gen_performance.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5497 pi->pcie_gen_performance.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5498 if (pi->pcie_lane_performance.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5499 pi->pcie_lane_performance.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5500 if (pi->pcie_lane_performance.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5501 pi->pcie_lane_performance.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5646 struct ci_power_info *pi; in ci_dpm_init() local
5650 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); in ci_dpm_init()
5651 if (pi == NULL) in ci_dpm_init()
5653 rdev->pm.dpm.priv = pi; in ci_dpm_init()
5657 pi->sys_pcie_mask = 0; in ci_dpm_init()
5659 pi->sys_pcie_mask = mask; in ci_dpm_init()
5660 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_dpm_init()
5662 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5663 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5664 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5665 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5667 pi->pcie_lane_performance.max = 0; in ci_dpm_init()
5668 pi->pcie_lane_performance.min = 16; in ci_dpm_init()
5669 pi->pcie_lane_powersaving.max = 0; in ci_dpm_init()
5670 pi->pcie_lane_powersaving.min = 16; in ci_dpm_init()
5672 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); in ci_dpm_init()
5696 pi->dll_default_on = false; in ci_dpm_init()
5697 pi->sram_end = SMC_RAM_END; in ci_dpm_init()
5699 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5700 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5701 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5702 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5703 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5704 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5705 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5706 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5708 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; in ci_dpm_init()
5710 pi->sclk_dpm_key_disabled = 0; in ci_dpm_init()
5711 pi->mclk_dpm_key_disabled = 0; in ci_dpm_init()
5712 pi->pcie_dpm_key_disabled = 0; in ci_dpm_init()
5713 pi->thermal_sclk_dpm_enabled = 0; in ci_dpm_init()
5718 pi->mclk_dpm_key_disabled = 1; in ci_dpm_init()
5721 pi->caps_sclk_ds = true; in ci_dpm_init()
5723 pi->mclk_strobe_mode_threshold = 40000; in ci_dpm_init()
5724 pi->mclk_stutter_mode_threshold = 40000; in ci_dpm_init()
5725 pi->mclk_edc_enable_threshold = 40000; in ci_dpm_init()
5726 pi->mclk_edc_wr_enable_threshold = 40000; in ci_dpm_init()
5730 pi->caps_fps = false; in ci_dpm_init()
5732 pi->caps_sclk_throttle_low_notification = false; in ci_dpm_init()
5734 pi->caps_uvd_dpm = true; in ci_dpm_init()
5735 pi->caps_vce_dpm = true; in ci_dpm_init()
5767 pi->thermal_temp_setting.temperature_low = 94500; in ci_dpm_init()
5768 pi->thermal_temp_setting.temperature_high = 95000; in ci_dpm_init()
5769 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5771 pi->thermal_temp_setting.temperature_low = 99500; in ci_dpm_init()
5772 pi->thermal_temp_setting.temperature_high = 100000; in ci_dpm_init()
5773 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5776 pi->uvd_enabled = false; in ci_dpm_init()
5778 dpm_table = &pi->smc_state_table; in ci_dpm_init()
5827 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5828 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5829 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5831 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5833 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5837 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5839 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5846 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5848 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5853 pi->vddc_phase_shed_control = true; in ci_dpm_init()
5856 pi->pcie_performance_request = in ci_dpm_init()
5859 pi->pcie_performance_request = false; in ci_dpm_init()
5864 pi->caps_sclk_ss_support = true; in ci_dpm_init()
5865 pi->caps_mclk_ss_support = true; in ci_dpm_init()
5866 pi->dynamic_ss = true; in ci_dpm_init()
5868 pi->caps_sclk_ss_support = false; in ci_dpm_init()
5869 pi->caps_mclk_ss_support = false; in ci_dpm_init()
5870 pi->dynamic_ss = true; in ci_dpm_init()
5874 pi->thermal_protection = true; in ci_dpm_init()
5876 pi->thermal_protection = false; in ci_dpm_init()
5878 pi->caps_dynamic_ac_timing = true; in ci_dpm_init()
5880 pi->uvd_power_gated = false; in ci_dpm_init()
5888 pi->fan_ctrl_is_in_default_mode = true; in ci_dpm_init()
5896 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_debugfs_print_current_performance_level() local
5897 struct radeon_ps *rps = &pi->current_rps; in ci_dpm_debugfs_print_current_performance_level()
5901 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); in ci_dpm_debugfs_print_current_performance_level()
5941 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_sclk() local
5942 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_sclk()
5952 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_mclk() local
5953 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_mclk()