335 	tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;  in ci_populate_tdc_limit()
416 	struct radeon_cac_tdp_table *cac_tdp_table =  in ci_populate_bapm_vddc_base_leakage_sidd()  local
417 		rdev->pm.dpm.dyn_state.cac_tdp_table;  in ci_populate_bapm_vddc_base_leakage_sidd()
419 	hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;  in ci_populate_bapm_vddc_base_leakage_sidd()
420 	lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;  in ci_populate_bapm_vddc_base_leakage_sidd()
433 	struct radeon_cac_tdp_table *cac_tdp_table =  in ci_populate_bapm_parameters_in_dpm_table()  local
434 		rdev->pm.dpm.dyn_state.cac_tdp_table;  in ci_populate_bapm_parameters_in_dpm_table()
440 	dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;  in ci_populate_bapm_parameters_in_dpm_table()
441 	dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;  in ci_populate_bapm_parameters_in_dpm_table()
668 					struct radeon_cac_tdp_table *cac_tdp_table =  in ci_enable_power_containment()  local
669 						rdev->pm.dpm.dyn_state.cac_tdp_table;  in ci_enable_power_containment()
671 						(u32)(cac_tdp_table->maximum_power_delivery_limit * 256);  in ci_enable_power_containment()
742 	struct radeon_cac_tdp_table *cac_tdp_table =  in ci_power_control_set_level()  local
743 		rdev->pm.dpm.dyn_state.cac_tdp_table;  in ci_power_control_set_level()
753 			      (s32)cac_tdp_table->configurable_tdp) / 100;  in ci_power_control_set_level()
1626 	struct radeon_cac_tdp_table *cac_tdp_table =
1627 		rdev->pm.dpm.dyn_state.cac_tdp_table;
1631 		power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1633 		power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);