235 		WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);  in atombios_blank_crtc()
244 		WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);  in atombios_blank_crtc()
399 			WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);  in atombios_disable_ss()
404 			WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);  in atombios_disable_ss()
415 			WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);  in atombios_disable_ss()
420 			WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);  in atombios_disable_ss()
1354 		WREG32(AVIVO_D1VGA_CONTROL, 0);  in dce4_crtc_do_set_base()
1357 		WREG32(AVIVO_D2VGA_CONTROL, 0);  in dce4_crtc_do_set_base()
1360 		WREG32(EVERGREEN_D3VGA_CONTROL, 0);  in dce4_crtc_do_set_base()
1363 		WREG32(EVERGREEN_D4VGA_CONTROL, 0);  in dce4_crtc_do_set_base()
1366 		WREG32(EVERGREEN_D5VGA_CONTROL, 0);  in dce4_crtc_do_set_base()
1369 		WREG32(EVERGREEN_D6VGA_CONTROL, 0);  in dce4_crtc_do_set_base()
1375 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1377 	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1379 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1381 	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1383 	WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);  in dce4_crtc_do_set_base()
1384 	WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);  in dce4_crtc_do_set_base()
1398 	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1399 	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1400 	WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1401 	WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1402 	WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);  in dce4_crtc_do_set_base()
1403 	WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);  in dce4_crtc_do_set_base()
1406 	WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);  in dce4_crtc_do_set_base()
1407 	WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);  in dce4_crtc_do_set_base()
1410 		WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1413 		WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1417 	WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1424 	WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1431 	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);  in dce4_crtc_do_set_base()
1434 	WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);  in dce4_crtc_do_set_base()
1577 		WREG32(AVIVO_D1VGA_CONTROL, 0);  in avivo_crtc_do_set_base()
1579 		WREG32(AVIVO_D2VGA_CONTROL, 0);  in avivo_crtc_do_set_base()
1583 			WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));  in avivo_crtc_do_set_base()
1584 			WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));  in avivo_crtc_do_set_base()
1586 			WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));  in avivo_crtc_do_set_base()
1587 			WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));  in avivo_crtc_do_set_base()
1590 	WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1592 	WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +  in avivo_crtc_do_set_base()
1594 	WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);  in avivo_crtc_do_set_base()
1596 		WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);  in avivo_crtc_do_set_base()
1605 	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);  in avivo_crtc_do_set_base()
1606 	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);  in avivo_crtc_do_set_base()
1607 	WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);  in avivo_crtc_do_set_base()
1608 	WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);  in avivo_crtc_do_set_base()
1609 	WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);  in avivo_crtc_do_set_base()
1610 	WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);  in avivo_crtc_do_set_base()
1613 	WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);  in avivo_crtc_do_set_base()
1614 	WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);  in avivo_crtc_do_set_base()
1616 	WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1620 	WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1624 	WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1631 	WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);  in avivo_crtc_do_set_base()
1634 	WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);  in avivo_crtc_do_set_base()
1693 		WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);  in radeon_legacy_atom_fixup()
1698 		WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);  in radeon_legacy_atom_fixup()
1699 		WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));  in radeon_legacy_atom_fixup()
1700 		WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));  in radeon_legacy_atom_fixup()
2160 		WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);  in atombios_crtc_disable()
2162 		WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);  in atombios_crtc_disable()