147 	struct nvkm_device *device = mmu->base.subdev.device;  in nv44_vm_flush()  local
148 	nvkm_wr32(device, 0x100814, mmu->base.limit - NV44_GART_PAGE);  in nv44_vm_flush()
149 	nvkm_wr32(device, 0x100808, 0x00000020);  in nv44_vm_flush()
150 	nvkm_msec(device, 2000,  in nv44_vm_flush()
151 		if (nvkm_rd32(device, 0x100808) & 0x00000001)  in nv44_vm_flush()
154 	nvkm_wr32(device, 0x100808, 0x00000000);  in nv44_vm_flush()
165 	struct nvkm_device *device = mmu->base.subdev.device;  in nv44_mmu_oneinit()  local
168 	mmu->nullp = dma_alloc_coherent(device->dev, 16 * 1024,  in nv44_mmu_oneinit()
180 	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,  in nv44_mmu_oneinit()
192 	struct nvkm_device *device = mmu->base.subdev.device;  in nv44_mmu_init()  local
200 	addr  = nvkm_rd32(device, 0x10020c);  in nv44_mmu_init()
203 	nvkm_wr32(device, 0x100850, 0x80000000);  in nv44_mmu_init()
204 	nvkm_wr32(device, 0x100818, mmu->null);  in nv44_mmu_init()
205 	nvkm_wr32(device, 0x100804, NV44_GART_SIZE);  in nv44_mmu_init()
206 	nvkm_wr32(device, 0x100850, 0x00008000);  in nv44_mmu_init()
207 	nvkm_mask(device, 0x10008c, 0x00000200, 0x00000200);  in nv44_mmu_init()
208 	nvkm_wr32(device, 0x100820, 0x00000000);  in nv44_mmu_init()
209 	nvkm_wr32(device, 0x10082c, 0x00000001);  in nv44_mmu_init()
210 	nvkm_wr32(device, 0x100800, addr | 0x00000010);  in nv44_mmu_init()
229 nv44_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)  in nv44_mmu_new()  argument
231 	if (device->type == NVKM_DEVICE_AGP ||  in nv44_mmu_new()
232 	    !nvkm_boolopt(device->cfgopt, "NvPCIE", true))  in nv44_mmu_new()
233 		return nv04_mmu_new(device, index, pmmu);  in nv44_mmu_new()
235 	return nv04_mmu_new_(&nv44_mmu, device, index, pmmu);  in nv44_mmu_new()