Lines Matching refs:mr
186 ram_mask(hwsq, mr[0], 0x100, 0x100); in nvkm_sddr2_dll_reset()
187 ram_mask(hwsq, mr[0], 0x100, 0x000); in nvkm_sddr2_dll_reset()
287 ram->base.mr[0] = ram_rd32(hwsq, mr[0]); in nv50_ram_calc()
288 ram->base.mr[1] = ram_rd32(hwsq, mr[1]); in nv50_ram_calc()
289 ram->base.mr[2] = ram_rd32(hwsq, mr[2]); in nv50_ram_calc()
377 ram_nuke(hwsq, mr[0]); /* force update */ in nv50_ram_calc()
378 ram_mask(hwsq, mr[0], 0x000, 0x000); in nv50_ram_calc()
381 ram_nuke(hwsq, mr[1]); /* force update */ in nv50_ram_calc()
382 ram_wr32(hwsq, mr[1], ram->base.mr[1]); in nv50_ram_calc()
383 ram_nuke(hwsq, mr[0]); /* force update */ in nv50_ram_calc()
384 ram_wr32(hwsq, mr[0], ram->base.mr[0]); in nv50_ram_calc()
454 ram_mask(hwsq, mr[1], 0xffffffff, ram->base.mr[1]); in nv50_ram_calc()