265 	if ((ram->base.mr[1] & 0x03c) != 0x030) {  in gk104_ram_calc_gddr5()
266 		ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c);  in gk104_ram_calc_gddr5()
267 		ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000);  in gk104_ram_calc_gddr5()
590 	ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]);  in gk104_ram_calc_gddr5()
591 	ram_wr32(fuc, mr[0], ram->base.mr[0]);  in gk104_ram_calc_gddr5()
592 	ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]);  in gk104_ram_calc_gddr5()
594 	ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]);  in gk104_ram_calc_gddr5()
595 	ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */  in gk104_ram_calc_gddr5()
596 	ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]);  in gk104_ram_calc_gddr5()
597 	ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]);  in gk104_ram_calc_gddr5()
649 	if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5])  in gk104_ram_calc_gddr5()
679 	ram_nuke(fuc, mr[0]);  in nvkm_sddr3_dll_reset()
680 	ram_mask(fuc, mr[0], 0x100, 0x100);  in nvkm_sddr3_dll_reset()
681 	ram_mask(fuc, mr[0], 0x100, 0x000);  in nvkm_sddr3_dll_reset()
687 	u32 mr1_old = ram_rd32(fuc, mr[1]);  in nvkm_sddr3_dll_disable()
690 		ram_mask(fuc, mr[1], 0x1, 0x1);  in nvkm_sddr3_dll_disable()
906 		ram_mask(fuc, mr[1], 0x1, 0x0);  in gk104_ram_calc_sddr3()
910 	ram_mask(fuc, mr[2], 0x00000fff, ram->base.mr[2]);  in gk104_ram_calc_sddr3()
911 	ram_mask(fuc, mr[1], 0xffffffff, ram->base.mr[1]);  in gk104_ram_calc_sddr3()
912 	ram_wr32(fuc, mr[0], ram->base.mr[0]);  in gk104_ram_calc_sddr3()
1081 		if (ram_have(fuc, mr[i]))  in gk104_ram_calc_xits()
1082 			ram->base.mr[i] = ram_rd32(fuc, mr[i]);  in gk104_ram_calc_xits()