127 	struct nvkm_device *device = clk->base.subdev.device;  in gk20a_pllg_read_mnp()  local
130 	val = nvkm_rd32(device, GPCPLL_COEFF);  in gk20a_pllg_read_mnp()
271 	struct nvkm_device *device = subdev->device;  in gk20a_pllg_slide()  local
276 	val = nvkm_rd32(device, GPCPLL_COEFF);  in gk20a_pllg_slide()
282 	nvkm_mask(device, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT,  in gk20a_pllg_slide()
284 	nvkm_mask(device, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT,  in gk20a_pllg_slide()
288 	nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,  in gk20a_pllg_slide()
293 	val = nvkm_rd32(device, GPCPLL_COEFF);  in gk20a_pllg_slide()
297 	nvkm_wr32(device, GPCPLL_COEFF, val);  in gk20a_pllg_slide()
300 	val = nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN);  in gk20a_pllg_slide()
303 	nvkm_wr32(device, GPCPLL_NDIV_SLOWDOWN, val);  in gk20a_pllg_slide()
307 		val = nvkm_rd32(device, GPC_BCAST_NDIV_SLOWDOWN_DEBUG);  in gk20a_pllg_slide()
313 	nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,  in gk20a_pllg_slide()
316 	nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN);  in gk20a_pllg_slide()
329 	struct nvkm_device *device = clk->base.subdev.device;  in _gk20a_pllg_enable()  local
330 	nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE);  in _gk20a_pllg_enable()
331 	nvkm_rd32(device, GPCPLL_CFG);  in _gk20a_pllg_enable()
337 	struct nvkm_device *device = clk->base.subdev.device;  in _gk20a_pllg_disable()  local
338 	nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0);  in _gk20a_pllg_disable()
339 	nvkm_rd32(device, GPCPLL_CFG);  in _gk20a_pllg_disable()
346 	struct nvkm_device *device = subdev->device;  in _gk20a_pllg_program_mnp()  local
351 	val = nvkm_rd32(device, GPCPLL_COEFF);  in _gk20a_pllg_program_mnp()
356 	cfg = nvkm_rd32(device, GPCPLL_CFG);  in _gk20a_pllg_program_mnp()
373 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,  in _gk20a_pllg_program_mnp()
377 	val = nvkm_rd32(device, SEL_VCO);  in _gk20a_pllg_program_mnp()
380 	nvkm_wr32(device, SEL_VCO, val);  in _gk20a_pllg_program_mnp()
383 	val = nvkm_rd32(device, GPCPLL_CFG);  in _gk20a_pllg_program_mnp()
386 		nvkm_wr32(device, GPCPLL_CFG, val);  in _gk20a_pllg_program_mnp()
387 		nvkm_rd32(device, GPCPLL_CFG);  in _gk20a_pllg_program_mnp()
401 	nvkm_wr32(device, GPCPLL_COEFF, val);  in _gk20a_pllg_program_mnp()
405 	val = nvkm_rd32(device, GPCPLL_CFG);  in _gk20a_pllg_program_mnp()
408 		nvkm_wr32(device, GPCPLL_CFG, val);  in _gk20a_pllg_program_mnp()
411 	if (nvkm_usec(device, 300,  in _gk20a_pllg_program_mnp()
412 		if (nvkm_rd32(device, GPCPLL_CFG) & GPCPLL_CFG_LOCK)  in _gk20a_pllg_program_mnp()
418 	nvkm_mask(device, SEL_VCO, 0, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT));  in _gk20a_pllg_program_mnp()
421 	val = nvkm_rd32(device, GPC2CLK_OUT);  in _gk20a_pllg_program_mnp()
424 	nvkm_wr32(device, GPC2CLK_OUT, val);  in _gk20a_pllg_program_mnp()
445 	struct nvkm_device *device = clk->base.subdev.device;  in gk20a_pllg_disable()  local
449 	val = nvkm_rd32(device, GPCPLL_CFG);  in gk20a_pllg_disable()
453 		coeff = nvkm_rd32(device, GPCPLL_COEFF);  in gk20a_pllg_disable()
461 	nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0);  in gk20a_pllg_disable()
567 	struct nvkm_device *device = subdev->device;  in gk20a_clk_read()  local
571 		return device->crystal;  in gk20a_clk_read()
615 	struct nvkm_device *device = subdev->device;  in gk20a_clk_init()  local
618 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL);  in gk20a_clk_init()
647 gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)  in gk20a_clk_new()  argument
649 	struct nvkm_device_tegra *tdev = device->func->tegra(device);  in gk20a_clk_new()
666 	ret = nvkm_clk_ctor(&gk20a_clk, device, index, true, &clk->base);  in gk20a_clk_new()