Lines Matching refs:gr
401 struct nv10_gr *gr; member
414 #define PIPE_SAVE(gr, state, addr) \ argument
422 #define PIPE_RESTORE(gr, state, addr) \ argument
434 struct nvkm_gr *gr = &chan->gr->base; in nv17_gr_mthd_lma_window() local
445 nv04_gr_idle(gr); in nv17_gr_mthd_lma_window()
452 nv04_gr_idle(gr); in nv17_gr_mthd_lma_window()
462 nv04_gr_idle(gr); in nv17_gr_mthd_lma_window()
485 nv04_gr_idle(gr); in nv17_gr_mthd_lma_window()
500 nv04_gr_idle(gr); in nv17_gr_mthd_lma_window()
507 struct nvkm_gr *gr = &chan->gr->base; in nv17_gr_mthd_lma_enable() local
509 nv04_gr_idle(gr); in nv17_gr_mthd_lma_enable()
547 nv10_gr_channel(struct nv10_gr *gr) in nv10_gr_channel() argument
549 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_channel()
553 if (chid < ARRAY_SIZE(gr->chan)) in nv10_gr_channel()
554 chan = gr->chan[chid]; in nv10_gr_channel()
562 struct nv10_gr *gr = chan->gr; in nv10_gr_save_pipe() local
564 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_save_pipe()
566 PIPE_SAVE(gr, pipe->pipe_0x4400, 0x4400); in nv10_gr_save_pipe()
567 PIPE_SAVE(gr, pipe->pipe_0x0200, 0x0200); in nv10_gr_save_pipe()
568 PIPE_SAVE(gr, pipe->pipe_0x6400, 0x6400); in nv10_gr_save_pipe()
569 PIPE_SAVE(gr, pipe->pipe_0x6800, 0x6800); in nv10_gr_save_pipe()
570 PIPE_SAVE(gr, pipe->pipe_0x6c00, 0x6c00); in nv10_gr_save_pipe()
571 PIPE_SAVE(gr, pipe->pipe_0x7000, 0x7000); in nv10_gr_save_pipe()
572 PIPE_SAVE(gr, pipe->pipe_0x7400, 0x7400); in nv10_gr_save_pipe()
573 PIPE_SAVE(gr, pipe->pipe_0x7800, 0x7800); in nv10_gr_save_pipe()
574 PIPE_SAVE(gr, pipe->pipe_0x0040, 0x0040); in nv10_gr_save_pipe()
575 PIPE_SAVE(gr, pipe->pipe_0x0000, 0x0000); in nv10_gr_save_pipe()
581 struct nv10_gr *gr = chan->gr; in nv10_gr_load_pipe() local
583 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_load_pipe()
587 nv04_gr_idle(&gr->base); in nv10_gr_load_pipe()
611 PIPE_RESTORE(gr, pipe->pipe_0x0200, 0x0200); in nv10_gr_load_pipe()
612 nv04_gr_idle(&gr->base); in nv10_gr_load_pipe()
617 PIPE_RESTORE(gr, pipe->pipe_0x6400, 0x6400); in nv10_gr_load_pipe()
618 PIPE_RESTORE(gr, pipe->pipe_0x6800, 0x6800); in nv10_gr_load_pipe()
619 PIPE_RESTORE(gr, pipe->pipe_0x6c00, 0x6c00); in nv10_gr_load_pipe()
620 PIPE_RESTORE(gr, pipe->pipe_0x7000, 0x7000); in nv10_gr_load_pipe()
621 PIPE_RESTORE(gr, pipe->pipe_0x7400, 0x7400); in nv10_gr_load_pipe()
622 PIPE_RESTORE(gr, pipe->pipe_0x7800, 0x7800); in nv10_gr_load_pipe()
623 PIPE_RESTORE(gr, pipe->pipe_0x4400, 0x4400); in nv10_gr_load_pipe()
624 PIPE_RESTORE(gr, pipe->pipe_0x0000, 0x0000); in nv10_gr_load_pipe()
625 PIPE_RESTORE(gr, pipe->pipe_0x0040, 0x0040); in nv10_gr_load_pipe()
626 nv04_gr_idle(&gr->base); in nv10_gr_load_pipe()
632 struct nv10_gr *gr = chan->gr; in nv10_gr_create_pipe() local
633 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in nv10_gr_create_pipe()
786 nv10_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg) in nv10_gr_ctx_regs_find_offset() argument
788 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in nv10_gr_ctx_regs_find_offset()
799 nv17_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg) in nv17_gr_ctx_regs_find_offset() argument
801 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in nv17_gr_ctx_regs_find_offset()
814 struct nv10_gr *gr = chan->gr; in nv10_gr_load_dma_vtxbuf() local
815 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_load_dma_vtxbuf()
885 struct nv10_gr *gr = chan->gr; in nv10_gr_load_context() local
886 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_load_context()
912 struct nv10_gr *gr = chan->gr; in nv10_gr_unload_context() local
913 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_unload_context()
932 nv10_gr_context_switch(struct nv10_gr *gr) in nv10_gr_context_switch() argument
934 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_context_switch()
939 nv04_gr_idle(&gr->base); in nv10_gr_context_switch()
942 prev = nv10_gr_channel(gr); in nv10_gr_context_switch()
948 next = gr->chan[chid]; in nv10_gr_context_switch()
957 struct nv10_gr *gr = chan->gr; in nv10_gr_chan_fini() local
958 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_chan_fini()
961 spin_lock_irqsave(&gr->lock, flags); in nv10_gr_chan_fini()
963 if (nv10_gr_channel(gr) == chan) in nv10_gr_chan_fini()
966 spin_unlock_irqrestore(&gr->lock, flags); in nv10_gr_chan_fini()
974 struct nv10_gr *gr = chan->gr; in nv10_gr_chan_dtor() local
977 spin_lock_irqsave(&gr->lock, flags); in nv10_gr_chan_dtor()
978 gr->chan[chan->chid] = NULL; in nv10_gr_chan_dtor()
979 spin_unlock_irqrestore(&gr->lock, flags); in nv10_gr_chan_dtor()
990 int offset = nv10_gr_ctx_regs_find_offset(gr, reg); \
996 int offset = nv17_gr_ctx_regs_find_offset(gr, reg); \
1005 struct nv10_gr *gr = nv10_gr(base); in nv10_gr_chan_new() local
1007 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_chan_new()
1013 chan->gr = gr; in nv10_gr_chan_new()
1038 spin_lock_irqsave(&gr->lock, flags); in nv10_gr_chan_new()
1039 gr->chan[chan->chid] = chan; in nv10_gr_chan_new()
1040 spin_unlock_irqrestore(&gr->lock, flags); in nv10_gr_chan_new()
1051 struct nv10_gr *gr = nv10_gr(base); in nv10_gr_tile() local
1052 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_tile()
1057 nv04_gr_idle(&gr->base); in nv10_gr_tile()
1083 struct nv10_gr *gr = nv10_gr(base); in nv10_gr_intr() local
1084 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in nv10_gr_intr()
1100 spin_lock_irqsave(&gr->lock, flags); in nv10_gr_intr()
1101 chan = gr->chan[chid]; in nv10_gr_intr()
1114 nv10_gr_context_switch(gr); in nv10_gr_intr()
1132 spin_unlock_irqrestore(&gr->lock, flags); in nv10_gr_intr()
1138 struct nv10_gr *gr = nv10_gr(base); in nv10_gr_init() local
1139 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_init()
1178 struct nv10_gr *gr; in nv10_gr_new_() local
1180 if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) in nv10_gr_new_()
1182 spin_lock_init(&gr->lock); in nv10_gr_new_()
1183 *pgr = &gr->base; in nv10_gr_new_()
1185 return nvkm_gr_ctor(func, device, index, 0x00001000, true, &gr->base); in nv10_gr_new_()