32 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gm20b_gr_init_gpc_mmu()  local
37 		nvkm_wr32(device, 0x100ce4, 0xffffffff);  in gm20b_gr_init_gpc_mmu()
41 	val = nvkm_rd32(device, 0x100c80);  in gm20b_gr_init_gpc_mmu()
43 	nvkm_wr32(device, 0x418880, val);  in gm20b_gr_init_gpc_mmu()
44 	nvkm_wr32(device, 0x418890, 0);  in gm20b_gr_init_gpc_mmu()
45 	nvkm_wr32(device, 0x418894, 0);  in gm20b_gr_init_gpc_mmu()
47 	nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));  in gm20b_gr_init_gpc_mmu()
48 	nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));  in gm20b_gr_init_gpc_mmu()
49 	nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));  in gm20b_gr_init_gpc_mmu()
51 	nvkm_wr32(device, 0x4188ac, nvkm_rd32(device, 0x100800));  in gm20b_gr_init_gpc_mmu()
57 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gm20b_gr_set_hww_esr_report_mask()  local
58 	nvkm_wr32(device, 0x419e44, 0xdffffe);  in gm20b_gr_set_hww_esr_report_mask()
59 	nvkm_wr32(device, 0x419e4c, 0x5);  in gm20b_gr_set_hww_esr_report_mask()
80 gm20b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)  in gm20b_gr_new()  argument
82 	return gk20a_gr_new_(&gm20b_gr, device, index, pgr);  in gm20b_gr_new()