46 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gf100_gr_zbc_clear_color()  local
48 		nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]);  in gf100_gr_zbc_clear_color()
49 		nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]);  in gf100_gr_zbc_clear_color()
50 		nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]);  in gf100_gr_zbc_clear_color()
51 		nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]);  in gf100_gr_zbc_clear_color()
53 	nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format);  in gf100_gr_zbc_clear_color()
54 	nvkm_wr32(device, 0x405820, zbc);  in gf100_gr_zbc_clear_color()
55 	nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */  in gf100_gr_zbc_clear_color()
62 	struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;  in gf100_gr_zbc_color_get()
97 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gf100_gr_zbc_clear_depth()  local
99 		nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds);  in gf100_gr_zbc_clear_depth()
100 	nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format);  in gf100_gr_zbc_clear_depth()
101 	nvkm_wr32(device, 0x405820, zbc);  in gf100_gr_zbc_clear_depth()
102 	nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */  in gf100_gr_zbc_clear_depth()
109 	struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;  in gf100_gr_zbc_depth_get()
233 gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data)  in gf100_gr_mthd_set_shader_exceptions()  argument
235 	nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000);  in gf100_gr_mthd_set_shader_exceptions()
236 	nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000);  in gf100_gr_mthd_set_shader_exceptions()
240 gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data)  in gf100_gr_mthd_sw()  argument
247 			gf100_gr_mthd_set_shader_exceptions(device, data);  in gf100_gr_mthd_sw()
287 	ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size,  in gf100_gr_chan_bind()
351 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gf100_gr_chan_new()  local
364 	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100,  in gf100_gr_chan_new()
378 		ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,  in gf100_gr_chan_new()
684 	struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;  in gf100_gr_zbc_init()
711 	struct nvkm_device *device = subdev->device;  in gf100_gr_wait_idle()  local
720 		nvkm_rd32(device, 0x400700);  in gf100_gr_wait_idle()
722 		gr_enabled = nvkm_rd32(device, 0x200) & 0x1000;  in gf100_gr_wait_idle()
723 		ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000;  in gf100_gr_wait_idle()
724 		gr_busy = nvkm_rd32(device, 0x40060c) & 0x1;  in gf100_gr_wait_idle()
739 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gf100_gr_mmio()  local
747 			nvkm_wr32(device, addr, init->data);  in gf100_gr_mmio()
756 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gf100_gr_icmd()  local
761 	nvkm_wr32(device, 0x400208, 0x80000000);  in gf100_gr_icmd()
768 			nvkm_wr32(device, 0x400204, init->data);  in gf100_gr_icmd()
773 			nvkm_wr32(device, 0x400200, addr);  in gf100_gr_icmd()
780 			nvkm_msec(device, 2000,  in gf100_gr_icmd()
781 				if (!(nvkm_rd32(device, 0x400700) & 0x00000004))  in gf100_gr_icmd()
788 	nvkm_wr32(device, 0x400208, 0x00000000);  in gf100_gr_icmd()
794 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gf100_gr_mthd()  local
805 			nvkm_wr32(device, 0x40448c, init->data);  in gf100_gr_mthd()
810 			nvkm_wr32(device, 0x404488, ctrl | (addr << 14));  in gf100_gr_mthd()
858 	struct nvkm_device *device = subdev->device;  in gf100_gr_trap_gpc_rop()  local
862 	trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff;  in gf100_gr_trap_gpc_rop()
863 	trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434));  in gf100_gr_trap_gpc_rop()
864 	trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438));  in gf100_gr_trap_gpc_rop()
865 	trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c));  in gf100_gr_trap_gpc_rop()
873 	nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);  in gf100_gr_trap_gpc_rop()
900 	struct nvkm_device *device = subdev->device;  in gf100_gr_trap_mp()  local
901 	u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648));  in gf100_gr_trap_mp()
902 	u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650));  in gf100_gr_trap_mp()
913 	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);  in gf100_gr_trap_mp()
914 	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr);  in gf100_gr_trap_mp()
921 	struct nvkm_device *device = subdev->device;  in gf100_gr_trap_tpc()  local
922 	u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508));  in gf100_gr_trap_tpc()
925 		u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224));  in gf100_gr_trap_tpc()
927 		nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);  in gf100_gr_trap_tpc()
937 		u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084));  in gf100_gr_trap_tpc()
939 		nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);  in gf100_gr_trap_tpc()
944 		u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c));  in gf100_gr_trap_tpc()
946 		nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);  in gf100_gr_trap_tpc()
959 	struct nvkm_device *device = subdev->device;  in gf100_gr_trap_gpc()  local
960 	u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90));  in gf100_gr_trap_gpc()
969 		u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900));  in gf100_gr_trap_gpc()
971 		nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);  in gf100_gr_trap_gpc()
976 		u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028));  in gf100_gr_trap_gpc()
978 		nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);  in gf100_gr_trap_gpc()
983 		u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824));  in gf100_gr_trap_gpc()
985 		nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);  in gf100_gr_trap_gpc()
993 			nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask);  in gf100_gr_trap_gpc()
1007 	struct nvkm_device *device = subdev->device;  in gf100_gr_trap_intr()  local
1008 	u32 trap = nvkm_rd32(device, 0x400108);  in gf100_gr_trap_intr()
1012 		u32 stat = nvkm_rd32(device, 0x404000);  in gf100_gr_trap_intr()
1014 		nvkm_wr32(device, 0x404000, 0xc0000000);  in gf100_gr_trap_intr()
1015 		nvkm_wr32(device, 0x400108, 0x00000001);  in gf100_gr_trap_intr()
1020 		u32 stat = nvkm_rd32(device, 0x404600);  in gf100_gr_trap_intr()
1022 		nvkm_wr32(device, 0x404600, 0xc0000000);  in gf100_gr_trap_intr()
1023 		nvkm_wr32(device, 0x400108, 0x00000002);  in gf100_gr_trap_intr()
1028 		u32 stat = nvkm_rd32(device, 0x408030);  in gf100_gr_trap_intr()
1030 		nvkm_wr32(device, 0x408030, 0xc0000000);  in gf100_gr_trap_intr()
1031 		nvkm_wr32(device, 0x400108, 0x00000008);  in gf100_gr_trap_intr()
1036 		u32 stat = nvkm_rd32(device, 0x405840);  in gf100_gr_trap_intr()
1038 		nvkm_wr32(device, 0x405840, 0xc0000000);  in gf100_gr_trap_intr()
1039 		nvkm_wr32(device, 0x400108, 0x00000010);  in gf100_gr_trap_intr()
1044 		u32 stat = nvkm_rd32(device, 0x40601c);  in gf100_gr_trap_intr()
1046 		nvkm_wr32(device, 0x40601c, 0xc0000000);  in gf100_gr_trap_intr()
1047 		nvkm_wr32(device, 0x400108, 0x00000040);  in gf100_gr_trap_intr()
1052 		u32 stat = nvkm_rd32(device, 0x404490);  in gf100_gr_trap_intr()
1054 		nvkm_wr32(device, 0x404490, 0xc0000000);  in gf100_gr_trap_intr()
1055 		nvkm_wr32(device, 0x400108, 0x00000080);  in gf100_gr_trap_intr()
1060 		u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff;  in gf100_gr_trap_intr()
1067 			nvkm_wr32(device, 0x407020, 0x40000000);  in gf100_gr_trap_intr()
1068 		nvkm_wr32(device, 0x400108, 0x00000100);  in gf100_gr_trap_intr()
1073 		u32 stat = nvkm_rd32(device, 0x400118);  in gf100_gr_trap_intr()
1078 				nvkm_wr32(device, 0x400118, mask);  in gf100_gr_trap_intr()
1082 		nvkm_wr32(device, 0x400108, 0x01000000);  in gf100_gr_trap_intr()
1088 			u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070));  in gf100_gr_trap_intr()
1089 			u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144));  in gf100_gr_trap_intr()
1092 			nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);  in gf100_gr_trap_intr()
1093 			nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);  in gf100_gr_trap_intr()
1095 		nvkm_wr32(device, 0x400108, 0x02000000);  in gf100_gr_trap_intr()
1101 		nvkm_wr32(device, 0x400108, trap);  in gf100_gr_trap_intr()
1109 	struct nvkm_device *device = subdev->device;  in gf100_gr_ctxctl_debug_unit()  local
1111 		   nvkm_rd32(device, base + 0x400));  in gf100_gr_ctxctl_debug_unit()
1113 		   nvkm_rd32(device, base + 0x800),  in gf100_gr_ctxctl_debug_unit()
1114 		   nvkm_rd32(device, base + 0x804),  in gf100_gr_ctxctl_debug_unit()
1115 		   nvkm_rd32(device, base + 0x808),  in gf100_gr_ctxctl_debug_unit()
1116 		   nvkm_rd32(device, base + 0x80c));  in gf100_gr_ctxctl_debug_unit()
1118 		   nvkm_rd32(device, base + 0x810),  in gf100_gr_ctxctl_debug_unit()
1119 		   nvkm_rd32(device, base + 0x814),  in gf100_gr_ctxctl_debug_unit()
1120 		   nvkm_rd32(device, base + 0x818),  in gf100_gr_ctxctl_debug_unit()
1121 		   nvkm_rd32(device, base + 0x81c));  in gf100_gr_ctxctl_debug_unit()
1127 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gf100_gr_ctxctl_debug()  local
1128 	u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff;  in gf100_gr_ctxctl_debug()
1140 	struct nvkm_device *device = subdev->device;  in gf100_gr_ctxctl_isr()  local
1141 	u32 stat = nvkm_rd32(device, 0x409c18);  in gf100_gr_ctxctl_isr()
1144 		u32 code = nvkm_rd32(device, 0x409814);  in gf100_gr_ctxctl_isr()
1146 			u32 class = nvkm_rd32(device, 0x409808);  in gf100_gr_ctxctl_isr()
1147 			u32  addr = nvkm_rd32(device, 0x40980c);  in gf100_gr_ctxctl_isr()
1150 			u32  data = nvkm_rd32(device, 0x409810);  in gf100_gr_ctxctl_isr()
1156 			nvkm_wr32(device, 0x409c20, 0x00000001);  in gf100_gr_ctxctl_isr()
1166 		nvkm_wr32(device, 0x409c20, 0x00080000);  in gf100_gr_ctxctl_isr()
1173 		nvkm_wr32(device, 0x409c20, stat);  in gf100_gr_ctxctl_isr()
1182 	struct nvkm_device *device = subdev->device;  in gf100_gr_intr()  local
1185 	u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff;  in gf100_gr_intr()
1186 	u32 stat = nvkm_rd32(device, 0x400100);  in gf100_gr_intr()
1187 	u32 addr = nvkm_rd32(device, 0x400704);  in gf100_gr_intr()
1190 	u32 data = nvkm_rd32(device, 0x400708);  in gf100_gr_intr()
1191 	u32 code = nvkm_rd32(device, 0x400110);  in gf100_gr_intr()
1196 	chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags);  in gf100_gr_intr()
1202 	if (device->card_type < NV_E0 || subc < 4)  in gf100_gr_intr()
1203 		class = nvkm_rd32(device, 0x404200 + (subc * 4));  in gf100_gr_intr()
1212 		nvkm_wr32(device, 0x400100, 0x00000001);  in gf100_gr_intr()
1217 		if (!gf100_gr_mthd_sw(device, class, mthd, data)) {  in gf100_gr_intr()
1223 		nvkm_wr32(device, 0x400100, 0x00000010);  in gf100_gr_intr()
1231 		nvkm_wr32(device, 0x400100, 0x00000020);  in gf100_gr_intr()
1242 		nvkm_wr32(device, 0x400100, 0x00100000);  in gf100_gr_intr()
1250 		nvkm_wr32(device, 0x400100, 0x00200000);  in gf100_gr_intr()
1256 		nvkm_wr32(device, 0x400100, 0x00080000);  in gf100_gr_intr()
1262 		nvkm_wr32(device, 0x400100, stat);  in gf100_gr_intr()
1265 	nvkm_wr32(device, 0x400500, 0x00010001);  in gf100_gr_intr()
1266 	nvkm_fifo_chan_put(device->fifo, flags, &chan);  in gf100_gr_intr()
1273 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gf100_gr_init_fw()  local
1276 	nvkm_wr32(device, fuc_base + 0x01c0, 0x01000000);  in gf100_gr_init_fw()
1278 		nvkm_wr32(device, fuc_base + 0x01c4, data->data[i]);  in gf100_gr_init_fw()
1280 	nvkm_wr32(device, fuc_base + 0x0180, 0x01000000);  in gf100_gr_init_fw()
1283 			nvkm_wr32(device, fuc_base + 0x0188, i >> 6);  in gf100_gr_init_fw()
1284 		nvkm_wr32(device, fuc_base + 0x0184, code->data[i]);  in gf100_gr_init_fw()
1289 		nvkm_wr32(device, fuc_base + 0x0184, 0);  in gf100_gr_init_fw()
1297 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gf100_gr_init_csdata()  local
1303 	nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar);  in gf100_gr_init_csdata()
1304 	star = nvkm_rd32(device, falcon + 0x01c4);  in gf100_gr_init_csdata()
1305 	temp = nvkm_rd32(device, falcon + 0x01c4);  in gf100_gr_init_csdata()
1308 	nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star);  in gf100_gr_init_csdata()
1317 					nvkm_wr32(device, falcon + 0x01c4, data);  in gf100_gr_init_csdata()
1329 	nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr);  in gf100_gr_init_csdata()
1330 	nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar);  in gf100_gr_init_csdata()
1331 	nvkm_wr32(device, falcon + 0x01c4, star + 4);  in gf100_gr_init_csdata()
1339 	struct nvkm_device *device = subdev->device;  in gf100_gr_init_ctxctl()  local
1344 		nvkm_mc_unk260(device->mc, 0);  in gf100_gr_init_ctxctl()
1347 		nvkm_mc_unk260(device->mc, 1);  in gf100_gr_init_ctxctl()
1350 		nvkm_wr32(device, 0x409840, 0xffffffff);  in gf100_gr_init_ctxctl()
1351 		nvkm_wr32(device, 0x41a10c, 0x00000000);  in gf100_gr_init_ctxctl()
1352 		nvkm_wr32(device, 0x40910c, 0x00000000);  in gf100_gr_init_ctxctl()
1353 		nvkm_wr32(device, 0x41a100, 0x00000002);  in gf100_gr_init_ctxctl()
1354 		nvkm_wr32(device, 0x409100, 0x00000002);  in gf100_gr_init_ctxctl()
1355 		if (nvkm_msec(device, 2000,  in gf100_gr_init_ctxctl()
1356 			if (nvkm_rd32(device, 0x409800) & 0x00000001)  in gf100_gr_init_ctxctl()
1361 		nvkm_wr32(device, 0x409840, 0xffffffff);  in gf100_gr_init_ctxctl()
1362 		nvkm_wr32(device, 0x409500, 0x7fffffff);  in gf100_gr_init_ctxctl()
1363 		nvkm_wr32(device, 0x409504, 0x00000021);  in gf100_gr_init_ctxctl()
1365 		nvkm_wr32(device, 0x409840, 0xffffffff);  in gf100_gr_init_ctxctl()
1366 		nvkm_wr32(device, 0x409500, 0x00000000);  in gf100_gr_init_ctxctl()
1367 		nvkm_wr32(device, 0x409504, 0x00000010);  in gf100_gr_init_ctxctl()
1368 		if (nvkm_msec(device, 2000,  in gf100_gr_init_ctxctl()
1369 			if ((gr->size = nvkm_rd32(device, 0x409800)))  in gf100_gr_init_ctxctl()
1374 		nvkm_wr32(device, 0x409840, 0xffffffff);  in gf100_gr_init_ctxctl()
1375 		nvkm_wr32(device, 0x409500, 0x00000000);  in gf100_gr_init_ctxctl()
1376 		nvkm_wr32(device, 0x409504, 0x00000016);  in gf100_gr_init_ctxctl()
1377 		if (nvkm_msec(device, 2000,  in gf100_gr_init_ctxctl()
1378 			if (nvkm_rd32(device, 0x409800))  in gf100_gr_init_ctxctl()
1383 		nvkm_wr32(device, 0x409840, 0xffffffff);  in gf100_gr_init_ctxctl()
1384 		nvkm_wr32(device, 0x409500, 0x00000000);  in gf100_gr_init_ctxctl()
1385 		nvkm_wr32(device, 0x409504, 0x00000025);  in gf100_gr_init_ctxctl()
1386 		if (nvkm_msec(device, 2000,  in gf100_gr_init_ctxctl()
1387 			if (nvkm_rd32(device, 0x409800))  in gf100_gr_init_ctxctl()
1392 		if (device->chipset >= 0xe0) {  in gf100_gr_init_ctxctl()
1393 			nvkm_wr32(device, 0x409800, 0x00000000);  in gf100_gr_init_ctxctl()
1394 			nvkm_wr32(device, 0x409500, 0x00000001);  in gf100_gr_init_ctxctl()
1395 			nvkm_wr32(device, 0x409504, 0x00000030);  in gf100_gr_init_ctxctl()
1396 			if (nvkm_msec(device, 2000,  in gf100_gr_init_ctxctl()
1397 				if (nvkm_rd32(device, 0x409800))  in gf100_gr_init_ctxctl()
1402 			nvkm_wr32(device, 0x409810, 0xb00095c8);  in gf100_gr_init_ctxctl()
1403 			nvkm_wr32(device, 0x409800, 0x00000000);  in gf100_gr_init_ctxctl()
1404 			nvkm_wr32(device, 0x409500, 0x00000001);  in gf100_gr_init_ctxctl()
1405 			nvkm_wr32(device, 0x409504, 0x00000031);  in gf100_gr_init_ctxctl()
1406 			if (nvkm_msec(device, 2000,  in gf100_gr_init_ctxctl()
1407 				if (nvkm_rd32(device, 0x409800))  in gf100_gr_init_ctxctl()
1412 			nvkm_wr32(device, 0x409810, 0x00080420);  in gf100_gr_init_ctxctl()
1413 			nvkm_wr32(device, 0x409800, 0x00000000);  in gf100_gr_init_ctxctl()
1414 			nvkm_wr32(device, 0x409500, 0x00000001);  in gf100_gr_init_ctxctl()
1415 			nvkm_wr32(device, 0x409504, 0x00000032);  in gf100_gr_init_ctxctl()
1416 			if (nvkm_msec(device, 2000,  in gf100_gr_init_ctxctl()
1417 				if (nvkm_rd32(device, 0x409800))  in gf100_gr_init_ctxctl()
1422 			nvkm_wr32(device, 0x409614, 0x00000070);  in gf100_gr_init_ctxctl()
1423 			nvkm_wr32(device, 0x409614, 0x00000770);  in gf100_gr_init_ctxctl()
1424 			nvkm_wr32(device, 0x40802c, 0x00000001);  in gf100_gr_init_ctxctl()
1442 	nvkm_mc_unk260(device->mc, 0);  in gf100_gr_init_ctxctl()
1443 	nvkm_wr32(device, 0x4091c0, 0x01000000);  in gf100_gr_init_ctxctl()
1445 		nvkm_wr32(device, 0x4091c4, gr->func->fecs.ucode->data.data[i]);  in gf100_gr_init_ctxctl()
1447 	nvkm_wr32(device, 0x409180, 0x01000000);  in gf100_gr_init_ctxctl()
1450 			nvkm_wr32(device, 0x409188, i >> 6);  in gf100_gr_init_ctxctl()
1451 		nvkm_wr32(device, 0x409184, gr->func->fecs.ucode->code.data[i]);  in gf100_gr_init_ctxctl()
1455 	nvkm_wr32(device, 0x41a1c0, 0x01000000);  in gf100_gr_init_ctxctl()
1457 		nvkm_wr32(device, 0x41a1c4, gr->func->gpccs.ucode->data.data[i]);  in gf100_gr_init_ctxctl()
1459 	nvkm_wr32(device, 0x41a180, 0x01000000);  in gf100_gr_init_ctxctl()
1462 			nvkm_wr32(device, 0x41a188, i >> 6);  in gf100_gr_init_ctxctl()
1463 		nvkm_wr32(device, 0x41a184, gr->func->gpccs.ucode->code.data[i]);  in gf100_gr_init_ctxctl()
1465 	nvkm_mc_unk260(device->mc, 1);  in gf100_gr_init_ctxctl()
1474 	nvkm_wr32(device, 0x40910c, 0x00000000);  in gf100_gr_init_ctxctl()
1475 	nvkm_wr32(device, 0x409100, 0x00000002);  in gf100_gr_init_ctxctl()
1476 	if (nvkm_msec(device, 2000,  in gf100_gr_init_ctxctl()
1477 		if (nvkm_rd32(device, 0x409800) & 0x80000000)  in gf100_gr_init_ctxctl()
1484 	gr->size = nvkm_rd32(device, 0x409804);  in gf100_gr_init_ctxctl()
1500 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gf100_gr_oneinit()  local
1503 	nvkm_pmu_pgob(device->pmu, false);  in gf100_gr_oneinit()
1505 	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false,  in gf100_gr_oneinit()
1510 	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false,  in gf100_gr_oneinit()
1525 	gr->rop_nr = (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16;  in gf100_gr_oneinit()
1526 	gr->gpc_nr =  nvkm_rd32(device, 0x409604) & 0x0000001f;  in gf100_gr_oneinit()
1528 		gr->tpc_nr[i]  = nvkm_rd32(device, GPC_UNIT(i, 0x2608));  in gf100_gr_oneinit()
1532 			u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4)));  in gf100_gr_oneinit()
1540 	switch (device->chipset) {  in gf100_gr_oneinit()
1585 	nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false);  in gf100_gr_init_()
1631 	struct nvkm_device *device = subdev->device;  in gf100_gr_ctor_fw()  local
1639 	strncpy(cname, device->chip->name, sizeof(cname));  in gf100_gr_ctor_fw()
1648 	ret = request_firmware(&fw, f, device->dev);  in gf100_gr_ctor_fw()
1661 gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device,  in gf100_gr_ctor()  argument
1667 	gr->firmware = nvkm_boolopt(device->cfgopt, "NvGrUseFW",  in gf100_gr_ctor()
1670 	ret = nvkm_gr_ctor(&gf100_gr_, device, index, 0x08001000,  in gf100_gr_ctor()
1689 gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device,  in gf100_gr_new_()  argument
1696 	return gf100_gr_ctor(func, device, index, gr);  in gf100_gr_new_()
1702 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gf100_gr_init()  local
1709 	nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000);  in gf100_gr_init()
1710 	nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000);  in gf100_gr_init()
1711 	nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000);  in gf100_gr_init()
1712 	nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000);  in gf100_gr_init()
1713 	nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000);  in gf100_gr_init()
1714 	nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000);  in gf100_gr_init()
1715 	nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8);  in gf100_gr_init()
1716 	nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8);  in gf100_gr_init()
1720 	nvkm_mask(device, TPC_UNIT(0, 0, 0x05c), 0x00000001, 0x00000001);  in gf100_gr_init()
1732 	nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);  in gf100_gr_init()
1733 	nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);  in gf100_gr_init()
1734 	nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);  in gf100_gr_init()
1735 	nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);  in gf100_gr_init()
1738 		nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),  in gf100_gr_init()
1740 		nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |  in gf100_gr_init()
1742 		nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);  in gf100_gr_init()
1745 	if (device->chipset != 0xd7)  in gf100_gr_init()
1746 		nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918);  in gf100_gr_init()
1748 		nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);  in gf100_gr_init()
1750 	nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));  in gf100_gr_init()
1752 	nvkm_wr32(device, 0x400500, 0x00010001);  in gf100_gr_init()
1754 	nvkm_wr32(device, 0x400100, 0xffffffff);  in gf100_gr_init()
1755 	nvkm_wr32(device, 0x40013c, 0xffffffff);  in gf100_gr_init()
1757 	nvkm_wr32(device, 0x409c24, 0x000f0000);  in gf100_gr_init()
1758 	nvkm_wr32(device, 0x404000, 0xc0000000);  in gf100_gr_init()
1759 	nvkm_wr32(device, 0x404600, 0xc0000000);  in gf100_gr_init()
1760 	nvkm_wr32(device, 0x408030, 0xc0000000);  in gf100_gr_init()
1761 	nvkm_wr32(device, 0x40601c, 0xc0000000);  in gf100_gr_init()
1762 	nvkm_wr32(device, 0x404490, 0xc0000000);  in gf100_gr_init()
1763 	nvkm_wr32(device, 0x406018, 0xc0000000);  in gf100_gr_init()
1764 	nvkm_wr32(device, 0x405840, 0xc0000000);  in gf100_gr_init()
1765 	nvkm_wr32(device, 0x405844, 0x00ffffff);  in gf100_gr_init()
1766 	nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);  in gf100_gr_init()
1767 	nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000);  in gf100_gr_init()
1770 		nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);  in gf100_gr_init()
1771 		nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);  in gf100_gr_init()
1772 		nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);  in gf100_gr_init()
1773 		nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);  in gf100_gr_init()
1775 			nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);  in gf100_gr_init()
1776 			nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);  in gf100_gr_init()
1777 			nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);  in gf100_gr_init()
1778 			nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);  in gf100_gr_init()
1779 			nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);  in gf100_gr_init()
1780 			nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);  in gf100_gr_init()
1781 			nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);  in gf100_gr_init()
1783 		nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);  in gf100_gr_init()
1784 		nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);  in gf100_gr_init()
1788 		nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);  in gf100_gr_init()
1789 		nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);  in gf100_gr_init()
1790 		nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);  in gf100_gr_init()
1791 		nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);  in gf100_gr_init()
1794 	nvkm_wr32(device, 0x400108, 0xffffffff);  in gf100_gr_init()
1795 	nvkm_wr32(device, 0x400138, 0xffffffff);  in gf100_gr_init()
1796 	nvkm_wr32(device, 0x400118, 0xffffffff);  in gf100_gr_init()
1797 	nvkm_wr32(device, 0x400130, 0xffffffff);  in gf100_gr_init()
1798 	nvkm_wr32(device, 0x40011c, 0xffffffff);  in gf100_gr_init()
1799 	nvkm_wr32(device, 0x400134, 0xffffffff);  in gf100_gr_init()
1801 	nvkm_wr32(device, 0x400054, 0x34ce3464);  in gf100_gr_init()
1845 gf100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)  in gf100_gr_new()  argument
1847 	return gf100_gr_new_(&gf100_gr, device, index, pgr);  in gf100_gr_new()