183 		u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04));  in gk104_fifo_intr_sched_ctxsw()  local
184 		u32 busy = (stat & 0x80000000);  in gk104_fifo_intr_sched_ctxsw()
185 		u32 next = (stat & 0x07ff0000) >> 16;  in gk104_fifo_intr_sched_ctxsw()
186 		u32 chsw = (stat & 0x00008000);  in gk104_fifo_intr_sched_ctxsw()
187 		u32 save = (stat & 0x00004000);  in gk104_fifo_intr_sched_ctxsw()
188 		u32 load = (stat & 0x00002000);  in gk104_fifo_intr_sched_ctxsw()
189 		u32 prev = (stat & 0x000007ff);  in gk104_fifo_intr_sched_ctxsw()
234 	u32 stat = nvkm_rd32(device, 0x00256c);  in gk104_fifo_intr_chsw()  local
235 	nvkm_error(subdev, "CHSW_ERROR %08x\n", stat);  in gk104_fifo_intr_chsw()
236 	nvkm_wr32(device, 0x00256c, stat);  in gk104_fifo_intr_chsw()
244 	u32 stat = nvkm_rd32(device, 0x00259c);  in gk104_fifo_intr_dropped_fault()  local
245 	nvkm_error(subdev, "DROPPED_MMU_FAULT %08x\n", stat);  in gk104_fifo_intr_dropped_fault()
361 	u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10));  in gk104_fifo_intr_fault()  local
362 	u32 gpc    = (stat & 0x1f000000) >> 24;  in gk104_fifo_intr_fault()
363 	u32 client = (stat & 0x00001f00) >> 8;  in gk104_fifo_intr_fault()
364 	u32 write  = (stat & 0x00000080);  in gk104_fifo_intr_fault()
365 	u32 hub    = (stat & 0x00000040);  in gk104_fifo_intr_fault()
366 	u32 reason = (stat & 0x0000000f);  in gk104_fifo_intr_fault()
455 	u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000)) & mask;  in gk104_fifo_intr_pbdma_0()  local
461 	u32 show = stat;  in gk104_fifo_intr_pbdma_0()
466 	if (stat & 0x00800000) {  in gk104_fifo_intr_pbdma_0()
485 	nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat);  in gk104_fifo_intr_pbdma_0()
503 	u32 stat = nvkm_rd32(device, 0x040148 + (unit * 0x2000)) & mask;  in gk104_fifo_intr_pbdma_1()  local
507 	if (stat) {  in gk104_fifo_intr_pbdma_1()
508 		nvkm_snprintbf(msg, sizeof(msg), gk104_fifo_pbdma_intr_1, stat);  in gk104_fifo_intr_pbdma_1()
510 			   unit, stat, msg, chid,  in gk104_fifo_intr_pbdma_1()
515 	nvkm_wr32(device, 0x040148 + (unit * 0x2000), stat);  in gk104_fifo_intr_pbdma_1()
544 	u32 stat = nvkm_rd32(device, 0x002100) & mask;  in gk104_fifo_intr()  local
546 	if (stat & 0x00000001) {  in gk104_fifo_intr()
549 		stat &= ~0x00000001;  in gk104_fifo_intr()
552 	if (stat & 0x00000010) {  in gk104_fifo_intr()
555 		stat &= ~0x00000010;  in gk104_fifo_intr()
558 	if (stat & 0x00000100) {  in gk104_fifo_intr()
561 		stat &= ~0x00000100;  in gk104_fifo_intr()
564 	if (stat & 0x00010000) {  in gk104_fifo_intr()
567 		stat &= ~0x00010000;  in gk104_fifo_intr()
570 	if (stat & 0x00800000) {  in gk104_fifo_intr()
573 		stat &= ~0x00800000;  in gk104_fifo_intr()
576 	if (stat & 0x01000000) {  in gk104_fifo_intr()
579 		stat &= ~0x01000000;  in gk104_fifo_intr()
582 	if (stat & 0x08000000) {  in gk104_fifo_intr()
585 		stat &= ~0x08000000;  in gk104_fifo_intr()
588 	if (stat & 0x10000000) {  in gk104_fifo_intr()
596 		stat &= ~0x10000000;  in gk104_fifo_intr()
599 	if (stat & 0x20000000) {  in gk104_fifo_intr()
608 		stat &= ~0x20000000;  in gk104_fifo_intr()
611 	if (stat & 0x40000000) {  in gk104_fifo_intr()
613 		stat &= ~0x40000000;  in gk104_fifo_intr()
616 	if (stat & 0x80000000) {  in gk104_fifo_intr()
619 		stat &= ~0x80000000;  in gk104_fifo_intr()
622 	if (stat) {  in gk104_fifo_intr()
623 		nvkm_error(subdev, "INTR %08x\n", stat);  in gk104_fifo_intr()
624 		nvkm_mask(device, 0x002140, stat, 0x00000000);  in gk104_fifo_intr()
625 		nvkm_wr32(device, 0x002100, stat);  in gk104_fifo_intr()