59 	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);  in nv40_fifo_dma_engine_fini()  local
60 	struct nv04_fifo *fifo = chan->fifo;  in nv40_fifo_dma_engine_fini()
74 	if (chid == chan->base.chid)  in nv40_fifo_dma_engine_fini()
77 	nvkm_wo32(imem->ramfc, chan->ramfc + ctx, 0x00000000);  in nv40_fifo_dma_engine_fini()
89 	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);  in nv40_fifo_dma_engine_init()  local
90 	struct nv04_fifo *fifo = chan->fifo;  in nv40_fifo_dma_engine_init()
99 	inst = chan->engn[engine->subdev.index]->addr >> 4;  in nv40_fifo_dma_engine_init()
105 	if (chid == chan->base.chid)  in nv40_fifo_dma_engine_init()
108 	nvkm_wo32(imem->ramfc, chan->ramfc + ctx, inst);  in nv40_fifo_dma_engine_init()
120 	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);  in nv40_fifo_dma_engine_dtor()  local
121 	nvkm_gpuobj_del(&chan->engn[engine->subdev.index]);  in nv40_fifo_dma_engine_dtor()
129 	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);  in nv40_fifo_dma_engine_ctor()  local
136 	return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]);  in nv40_fifo_dma_engine_ctor()
143 	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);  in nv40_fifo_dma_object_ctor()  local
144 	struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem;  in nv40_fifo_dma_object_ctor()
145 	u32 context = chan->base.chid << 23;  in nv40_fifo_dma_object_ctor()
159 	mutex_lock(&chan->fifo->base.engine.subdev.mutex);  in nv40_fifo_dma_object_ctor()
160 	hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4,  in nv40_fifo_dma_object_ctor()
162 	mutex_unlock(&chan->fifo->base.engine.subdev.mutex);  in nv40_fifo_dma_object_ctor()
188 	struct nv04_fifo_chan *chan = NULL;  in nv40_fifo_dma_new()  local
203 	if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))  in nv40_fifo_dma_new()
205 	*pobject = &chan->base.object;  in nv40_fifo_dma_new()
213 				  0, 0xc00000, 0x1000, oclass, &chan->base);  in nv40_fifo_dma_new()
214 	chan->fifo = fifo;  in nv40_fifo_dma_new()
218 	args->v0.chid = chan->base.chid;  in nv40_fifo_dma_new()
219 	chan->ramfc = chan->base.chid * 128;  in nv40_fifo_dma_new()
222 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);  in nv40_fifo_dma_new()
223 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);  in nv40_fifo_dma_new()
224 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4);  in nv40_fifo_dma_new()
225 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x18, 0x30000000 |  in nv40_fifo_dma_new()
232 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x3c, 0x0001ffff);  in nv40_fifo_dma_new()