37 	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);  in nv04_fifo_dma_object_dtor()  local
38 	struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem;  in nv04_fifo_dma_object_dtor()
46 	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);  in nv04_fifo_dma_object_ctor()  local
47 	struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem;  in nv04_fifo_dma_object_ctor()
48 	u32 context = 0x80000000 | chan->base.chid << 24;  in nv04_fifo_dma_object_ctor()
62 	mutex_lock(&chan->fifo->base.engine.subdev.mutex);  in nv04_fifo_dma_object_ctor()
63 	hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4,  in nv04_fifo_dma_object_ctor()
65 	mutex_unlock(&chan->fifo->base.engine.subdev.mutex);  in nv04_fifo_dma_object_ctor()
72 	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);  in nv04_fifo_dma_fini()  local
73 	struct nv04_fifo *fifo = chan->fifo;  in nv04_fifo_dma_fini()
79 	u32 data = chan->ramfc;  in nv04_fifo_dma_fini()
88 	if (chid == chan->base.chid) {  in nv04_fifo_dma_fini()
115 	nvkm_mask(device, NV04_PFIFO_MODE, 1 << chan->base.chid, 0);  in nv04_fifo_dma_fini()
123 	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);  in nv04_fifo_dma_init()  local
124 	struct nv04_fifo *fifo = chan->fifo;  in nv04_fifo_dma_init()
126 	u32 mask = 1 << chan->base.chid;  in nv04_fifo_dma_init()
136 	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);  in nv04_fifo_dma_dtor()  local
137 	struct nv04_fifo *fifo = chan->fifo;  in nv04_fifo_dma_dtor()
143 		nvkm_wo32(imem->ramfc, chan->ramfc + c->ctxp, 0x00000000);  in nv04_fifo_dma_dtor()
146 	return chan;  in nv04_fifo_dma_dtor()
167 	struct nv04_fifo_chan *chan = NULL;  in nv04_fifo_dma_new()  local
182 	if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))  in nv04_fifo_dma_new()
184 	*pobject = &chan->base.object;  in nv04_fifo_dma_new()
191 				  0, 0x800000, 0x10000, oclass, &chan->base);  in nv04_fifo_dma_new()
192 	chan->fifo = fifo;  in nv04_fifo_dma_new()
196 	args->v0.chid = chan->base.chid;  in nv04_fifo_dma_new()
197 	chan->ramfc = chan->base.chid * 32;  in nv04_fifo_dma_new()
200 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);  in nv04_fifo_dma_new()
201 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);  in nv04_fifo_dma_new()
202 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x08, chan->base.push->addr >> 4);  in nv04_fifo_dma_new()
203 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x10,  in nv04_fifo_dma_new()