34 g84_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type,  in g84_fifo_chan_ntfy()  argument
39 		*pevent = &chan->fifo->uevent;  in g84_fifo_chan_ntfy()
93 	struct nv50_fifo_chan *chan = nv50_fifo_chan(base);  in g84_fifo_chan_engine_fini()  local
94 	struct nv50_fifo *fifo = chan->fifo;  in g84_fifo_chan_engine_fini()
107 	nvkm_wr32(device, 0x0032fc, chan->base.inst->addr >> 12);  in g84_fifo_chan_engine_fini()
115 			   chan->base.chid, chan->base.object.client->name);  in g84_fifo_chan_engine_fini()
120 	nvkm_kmap(chan->eng);  in g84_fifo_chan_engine_fini()
121 	nvkm_wo32(chan->eng, offset + 0x00, 0x00000000);  in g84_fifo_chan_engine_fini()
122 	nvkm_wo32(chan->eng, offset + 0x04, 0x00000000);  in g84_fifo_chan_engine_fini()
123 	nvkm_wo32(chan->eng, offset + 0x08, 0x00000000);  in g84_fifo_chan_engine_fini()
124 	nvkm_wo32(chan->eng, offset + 0x0c, 0x00000000);  in g84_fifo_chan_engine_fini()
125 	nvkm_wo32(chan->eng, offset + 0x10, 0x00000000);  in g84_fifo_chan_engine_fini()
126 	nvkm_wo32(chan->eng, offset + 0x14, 0x00000000);  in g84_fifo_chan_engine_fini()
127 	nvkm_done(chan->eng);  in g84_fifo_chan_engine_fini()
136 	struct nv50_fifo_chan *chan = nv50_fifo_chan(base);  in g84_fifo_chan_engine_init()  local
137 	struct nvkm_gpuobj *engn = chan->engn[engine->subdev.index];  in g84_fifo_chan_engine_init()
147 	nvkm_kmap(chan->eng);  in g84_fifo_chan_engine_init()
148 	nvkm_wo32(chan->eng, offset + 0x00, 0x00190000);  in g84_fifo_chan_engine_init()
149 	nvkm_wo32(chan->eng, offset + 0x04, lower_32_bits(limit));  in g84_fifo_chan_engine_init()
150 	nvkm_wo32(chan->eng, offset + 0x08, lower_32_bits(start));  in g84_fifo_chan_engine_init()
151 	nvkm_wo32(chan->eng, offset + 0x0c, upper_32_bits(limit) << 24 |  in g84_fifo_chan_engine_init()
153 	nvkm_wo32(chan->eng, offset + 0x10, 0x00000000);  in g84_fifo_chan_engine_init()
154 	nvkm_wo32(chan->eng, offset + 0x14, 0x00000000);  in g84_fifo_chan_engine_init()
155 	nvkm_done(chan->eng);  in g84_fifo_chan_engine_init()
164 	struct nv50_fifo_chan *chan = nv50_fifo_chan(base);  in g84_fifo_chan_engine_ctor()  local
170 	return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]);  in g84_fifo_chan_engine_ctor()
177 	struct nv50_fifo_chan *chan = nv50_fifo_chan(base);  in g84_fifo_chan_object_ctor()  local
201 	return nvkm_ramht_insert(chan->ramht, object, 0, 4, handle, context);  in g84_fifo_chan_object_ctor()
207 	struct nv50_fifo_chan *chan = nv50_fifo_chan(base);  in g84_fifo_chan_init()  local
208 	struct nv50_fifo *fifo = chan->fifo;  in g84_fifo_chan_init()
210 	u64 addr = chan->ramfc->addr >> 8;  in g84_fifo_chan_init()
211 	u32 chid = chan->base.chid;  in g84_fifo_chan_init()
234 		   struct nv50_fifo_chan *chan)  in g84_fifo_chan_ctor()  argument
255 				  0, 0xc00000, 0x2000, oclass, &chan->base);  in g84_fifo_chan_ctor()
256 	chan->fifo = fifo;  in g84_fifo_chan_ctor()
260 	ret = nvkm_gpuobj_new(device, 0x0200, 0, true, chan->base.inst,  in g84_fifo_chan_ctor()
261 			      &chan->eng);  in g84_fifo_chan_ctor()
265 	ret = nvkm_gpuobj_new(device, 0x4000, 0, false, chan->base.inst,  in g84_fifo_chan_ctor()
266 			      &chan->pgd);  in g84_fifo_chan_ctor()
270 	ret = nvkm_gpuobj_new(device, 0x1000, 0x400, true, chan->base.inst,  in g84_fifo_chan_ctor()
271 			      &chan->cache);  in g84_fifo_chan_ctor()
275 	ret = nvkm_gpuobj_new(device, 0x100, 0x100, true, chan->base.inst,  in g84_fifo_chan_ctor()
276 			      &chan->ramfc);  in g84_fifo_chan_ctor()
280 	ret = nvkm_ramht_new(device, 0x8000, 16, chan->base.inst, &chan->ramht);  in g84_fifo_chan_ctor()
284 	return nvkm_vm_ref(chan->base.vm, &chan->vm, chan->pgd);  in g84_fifo_chan_ctor()