37 	struct nvkm_device *device = disp->base.engine.subdev.device;  in nv50_disp_root_scanoutpos()  local
38 	const u32 blanke = nvkm_rd32(device, 0x610aec + (head * 0x540));  in nv50_disp_root_scanoutpos()
39 	const u32 blanks = nvkm_rd32(device, 0x610af4 + (head * 0x540));  in nv50_disp_root_scanoutpos()
40 	const u32 total  = nvkm_rd32(device, 0x610afc + (head * 0x540));  in nv50_disp_root_scanoutpos()
58 			nvkm_rd32(device, 0x616340 + (head * 0x800)) & 0xffff;  in nv50_disp_root_scanoutpos()
61 			nvkm_rd32(device, 0x616344 + (head * 0x800)) & 0xffff;  in nv50_disp_root_scanoutpos()
277 	struct nvkm_device *device = disp->base.engine.subdev.device;  in nv50_disp_root_new_()  local
288 	ret = nvkm_gpuobj_new(disp->base.engine.subdev.device, 0x10000, 0x10000,  in nv50_disp_root_new_()
293 	return nvkm_ramht_new(device, 0x1000, 0, root->instmem, &root->ramht);  in nv50_disp_root_new_()
299 	struct nvkm_device *device = root->disp->base.engine.subdev.device;  in nv50_disp_root_fini()  local
301 	nvkm_wr32(device, 0x610024, 0x00000000);  in nv50_disp_root_fini()
302 	nvkm_wr32(device, 0x610020, 0x00000000);  in nv50_disp_root_fini()
309 	struct nvkm_device *device = disp->base.engine.subdev.device;  in nv50_disp_root_init()  local
317 	tmp = nvkm_rd32(device, 0x614004);  in nv50_disp_root_init()
318 	nvkm_wr32(device, 0x610184, tmp);  in nv50_disp_root_init()
322 		tmp = nvkm_rd32(device, 0x616100 + (i * 0x800));  in nv50_disp_root_init()
323 		nvkm_wr32(device, 0x610190 + (i * 0x10), tmp);  in nv50_disp_root_init()
324 		tmp = nvkm_rd32(device, 0x616104 + (i * 0x800));  in nv50_disp_root_init()
325 		nvkm_wr32(device, 0x610194 + (i * 0x10), tmp);  in nv50_disp_root_init()
326 		tmp = nvkm_rd32(device, 0x616108 + (i * 0x800));  in nv50_disp_root_init()
327 		nvkm_wr32(device, 0x610198 + (i * 0x10), tmp);  in nv50_disp_root_init()
328 		tmp = nvkm_rd32(device, 0x61610c + (i * 0x800));  in nv50_disp_root_init()
329 		nvkm_wr32(device, 0x61019c + (i * 0x10), tmp);  in nv50_disp_root_init()
334 		tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800));  in nv50_disp_root_init()
335 		nvkm_wr32(device, 0x6101d0 + (i * 0x04), tmp);  in nv50_disp_root_init()
340 		tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));  in nv50_disp_root_init()
341 		nvkm_wr32(device, 0x6101e0 + (i * 0x04), tmp);  in nv50_disp_root_init()
346 		tmp = nvkm_rd32(device, 0x61e000 + (i * 0x800));  in nv50_disp_root_init()
347 		nvkm_wr32(device, 0x6101f0 + (i * 0x04), tmp);  in nv50_disp_root_init()
351 	if (nvkm_rd32(device, 0x610024) & 0x00000100) {  in nv50_disp_root_init()
352 		nvkm_wr32(device, 0x610024, 0x00000100);  in nv50_disp_root_init()
353 		nvkm_mask(device, 0x6194e8, 0x00000001, 0x00000000);  in nv50_disp_root_init()
354 		if (nvkm_msec(device, 2000,  in nv50_disp_root_init()
355 			if (!(nvkm_rd32(device, 0x6194e8) & 0x00000002))  in nv50_disp_root_init()
362 	nvkm_wr32(device, 0x610010, (root->instmem->addr >> 8) | 9);  in nv50_disp_root_init()
365 	nvkm_wr32(device, 0x61002c, 0x00000370);  in nv50_disp_root_init()
366 	nvkm_wr32(device, 0x610028, 0x00000000);  in nv50_disp_root_init()