34 	struct nvkm_device *device = disp->base.engine.subdev.device;  in g84_hdmi_ctrl()  local
58 		nvkm_mask(device, 0x6165a4 + hoff, 0x40000000, 0x00000000);  in g84_hdmi_ctrl()
59 		nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000);  in g84_hdmi_ctrl()
60 		nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000);  in g84_hdmi_ctrl()
65 	nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000);  in g84_hdmi_ctrl()
66 	nvkm_wr32(device, 0x616528 + hoff, 0x000d0282);  in g84_hdmi_ctrl()
67 	nvkm_wr32(device, 0x61652c + hoff, 0x0000006f);  in g84_hdmi_ctrl()
68 	nvkm_wr32(device, 0x616530 + hoff, 0x00000000);  in g84_hdmi_ctrl()
69 	nvkm_wr32(device, 0x616534 + hoff, 0x00000000);  in g84_hdmi_ctrl()
70 	nvkm_wr32(device, 0x616538 + hoff, 0x00000000);  in g84_hdmi_ctrl()
71 	nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000001);  in g84_hdmi_ctrl()
74 	nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000);  in g84_hdmi_ctrl()
75 	nvkm_wr32(device, 0x616508 + hoff, 0x000a0184);  in g84_hdmi_ctrl()
76 	nvkm_wr32(device, 0x61650c + hoff, 0x00000071);  in g84_hdmi_ctrl()
77 	nvkm_wr32(device, 0x616510 + hoff, 0x00000000);  in g84_hdmi_ctrl()
78 	nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000001);  in g84_hdmi_ctrl()
80 	nvkm_mask(device, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */  in g84_hdmi_ctrl()
81 	nvkm_mask(device, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */  in g84_hdmi_ctrl()
82 	nvkm_mask(device, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */  in g84_hdmi_ctrl()
85 	nvkm_mask(device, 0x61733c, 0x00100000, 0x00100000); /* RESETF */  in g84_hdmi_ctrl()
86 	nvkm_mask(device, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */  in g84_hdmi_ctrl()
87 	nvkm_mask(device, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */  in g84_hdmi_ctrl()
90 	nvkm_mask(device, 0x6165a4 + hoff, 0x5f1f007f, ctrl);  in g84_hdmi_ctrl()