192 	struct nvif_object sync;  member
207 	nvif_object_fini(&dmac->sync);  in nv50_dmac_destroy()
258 			       &dmac->sync);  in nv50_dmac_create()
376 	struct nv50_sync sync;  member
383 #define nv50_sync(c) (&nv50_head(c)->sync)
401 	struct nouveau_bo *sync;  member
489 		nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);  in evo_sync()
497 			if (evo_sync_wait(disp->sync))  in evo_sync()
512 	return nv50_disp(dev)->sync;  in nv50_display_crtc_sema()
524 	if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==  in nv50_display_flip_wait()
567 	struct nv50_sync *sync = nv50_sync(crtc);  in nv50_display_flip_next()  local
581 	push = evo_wait(sync, 128);  in nv50_display_flip_next()
592 		OUT_RING  (chan, sync->addr ^ 0x10);  in nv50_display_flip_next()
594 		OUT_RING  (chan, sync->data + 1);  in nv50_display_flip_next()
596 		OUT_RING  (chan, sync->addr);  in nv50_display_flip_next()
597 		OUT_RING  (chan, sync->data);  in nv50_display_flip_next()
600 		u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;  in nv50_display_flip_next()
610 		OUT_RING  (chan, sync->data + 1);  in nv50_display_flip_next()
615 		OUT_RING  (chan, sync->data);  in nv50_display_flip_next()
619 		u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;  in nv50_display_flip_next()
627 		OUT_RING  (chan, sync->data + 1);  in nv50_display_flip_next()
633 		OUT_RING  (chan, sync->data);  in nv50_display_flip_next()
639 		sync->addr ^= 0x10;  in nv50_display_flip_next()
640 		sync->data++;  in nv50_display_flip_next()
654 	evo_data(push, sync->addr);  in nv50_display_flip_next()
655 	evo_data(push, sync->data++);  in nv50_display_flip_next()
656 	evo_data(push, sync->data);  in nv50_display_flip_next()
657 	evo_data(push, sync->base.sync.handle);  in nv50_display_flip_next()
666 	if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) {  in nv50_display_flip_next()
683 	evo_kick(push, sync);  in nv50_display_flip_next()
1382 	nv50_dmac_destroy(&head->sync.base, disp->disp);  in nv50_crtc_destroy()
1481 	ret = nv50_base_create(device, disp->disp, index, disp->sync->bo.offset,  in nv50_crtc_create()
1482 			       &head->sync);  in nv50_crtc_create()
1486 	head->sync.addr = EVO_FLIP_SEM0(index);  in nv50_crtc_create()
1487 	head->sync.data = 0x00000000;  in nv50_crtc_create()
1494 	ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset,  in nv50_crtc_create()
2384 		int ret = nvif_object_init(&head->sync.base.base.user, name,  in nv50_fbdma_init()
2472 		struct nv50_sync *sync = nv50_sync(crtc);  in nv50_display_init()  local
2475 		nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);  in nv50_display_init()
2479 	evo_data(push, nv50_mast(dev)->base.sync.handle);  in nv50_display_init()
2496 	nouveau_bo_unmap(disp->sync);  in nv50_display_destroy()
2497 	if (disp->sync)  in nv50_display_destroy()
2498 		nouveau_bo_unpin(disp->sync);  in nv50_display_destroy()
2499 	nouveau_bo_ref(NULL, &disp->sync);  in nv50_display_destroy()
2531 			     0, 0x0000, NULL, NULL, &disp->sync);  in nv50_display_create()
2533 		ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);  in nv50_display_create()
2535 			ret = nouveau_bo_map(disp->sync);  in nv50_display_create()
2537 				nouveau_bo_unpin(disp->sync);  in nv50_display_create()
2540 			nouveau_bo_ref(NULL, &disp->sync);  in nv50_display_create()
2547 	ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset,  in nv50_display_create()