Lines Matching refs:args
94 struct nv_dma_v0 args = {}; in nouveau_channel_prep() local
138 args.target = NV_DMA_V0_TARGET_VM; in nouveau_channel_prep()
139 args.access = NV_DMA_V0_ACCESS_VM; in nouveau_channel_prep()
140 args.start = 0; in nouveau_channel_prep()
141 args.limit = cli->vm->mmu->limit - 1; in nouveau_channel_prep()
149 args.target = NV_DMA_V0_TARGET_PCI; in nouveau_channel_prep()
150 args.access = NV_DMA_V0_ACCESS_RDWR; in nouveau_channel_prep()
151 args.start = nvxx_device(device)->func-> in nouveau_channel_prep()
153 args.limit = args.start + device->info.ram_user - 1; in nouveau_channel_prep()
155 args.target = NV_DMA_V0_TARGET_VRAM; in nouveau_channel_prep()
156 args.access = NV_DMA_V0_ACCESS_RDWR; in nouveau_channel_prep()
157 args.start = 0; in nouveau_channel_prep()
158 args.limit = device->info.ram_user - 1; in nouveau_channel_prep()
162 args.target = NV_DMA_V0_TARGET_AGP; in nouveau_channel_prep()
163 args.access = NV_DMA_V0_ACCESS_RDWR; in nouveau_channel_prep()
164 args.start = chan->drm->agp.base; in nouveau_channel_prep()
165 args.limit = chan->drm->agp.base + in nouveau_channel_prep()
168 args.target = NV_DMA_V0_TARGET_VM; in nouveau_channel_prep()
169 args.access = NV_DMA_V0_ACCESS_RDWR; in nouveau_channel_prep()
170 args.start = 0; in nouveau_channel_prep()
171 args.limit = mmu->limit - 1; in nouveau_channel_prep()
176 &args, sizeof(args), &chan->push.ctxdma); in nouveau_channel_prep()
200 } args; in nouveau_channel_ind() local
214 args.kepler.version = 0; in nouveau_channel_ind()
215 args.kepler.engine = engine; in nouveau_channel_ind()
216 args.kepler.ilength = 0x02000; in nouveau_channel_ind()
217 args.kepler.ioffset = 0x10000 + chan->push.vma.offset; in nouveau_channel_ind()
218 args.kepler.vm = 0; in nouveau_channel_ind()
219 size = sizeof(args.kepler); in nouveau_channel_ind()
222 args.fermi.version = 0; in nouveau_channel_ind()
223 args.fermi.ilength = 0x02000; in nouveau_channel_ind()
224 args.fermi.ioffset = 0x10000 + chan->push.vma.offset; in nouveau_channel_ind()
225 args.fermi.vm = 0; in nouveau_channel_ind()
226 size = sizeof(args.fermi); in nouveau_channel_ind()
228 args.nv50.version = 0; in nouveau_channel_ind()
229 args.nv50.ilength = 0x02000; in nouveau_channel_ind()
230 args.nv50.ioffset = 0x10000 + chan->push.vma.offset; in nouveau_channel_ind()
231 args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma); in nouveau_channel_ind()
232 args.nv50.vm = 0; in nouveau_channel_ind()
233 size = sizeof(args.nv50); in nouveau_channel_ind()
237 &args, size, &chan->user); in nouveau_channel_ind()
240 chan->chid = args.kepler.chid; in nouveau_channel_ind()
243 chan->chid = args.fermi.chid; in nouveau_channel_ind()
245 chan->chid = args.nv50.chid; in nouveau_channel_ind()
264 struct nv03_channel_dma_v0 args; in nouveau_channel_dma() local
275 args.version = 0; in nouveau_channel_dma()
276 args.pushbuf = nvif_handle(&chan->push.ctxdma); in nouveau_channel_dma()
277 args.offset = chan->push.vma.offset; in nouveau_channel_dma()
281 &args, sizeof(args), &chan->user); in nouveau_channel_dma()
283 chan->chid = args.chid; in nouveau_channel_dma()
298 struct nv_dma_v0 args = {}; in nouveau_channel_init() local
306 args.target = NV_DMA_V0_TARGET_VM; in nouveau_channel_init()
307 args.access = NV_DMA_V0_ACCESS_VM; in nouveau_channel_init()
308 args.start = 0; in nouveau_channel_init()
309 args.limit = cli->vm->mmu->limit - 1; in nouveau_channel_init()
311 args.target = NV_DMA_V0_TARGET_VRAM; in nouveau_channel_init()
312 args.access = NV_DMA_V0_ACCESS_RDWR; in nouveau_channel_init()
313 args.start = 0; in nouveau_channel_init()
314 args.limit = device->info.ram_user - 1; in nouveau_channel_init()
318 &args, sizeof(args), &chan->vram); in nouveau_channel_init()
323 args.target = NV_DMA_V0_TARGET_VM; in nouveau_channel_init()
324 args.access = NV_DMA_V0_ACCESS_VM; in nouveau_channel_init()
325 args.start = 0; in nouveau_channel_init()
326 args.limit = cli->vm->mmu->limit - 1; in nouveau_channel_init()
329 args.target = NV_DMA_V0_TARGET_AGP; in nouveau_channel_init()
330 args.access = NV_DMA_V0_ACCESS_RDWR; in nouveau_channel_init()
331 args.start = chan->drm->agp.base; in nouveau_channel_init()
332 args.limit = chan->drm->agp.base + in nouveau_channel_init()
335 args.target = NV_DMA_V0_TARGET_VM; in nouveau_channel_init()
336 args.access = NV_DMA_V0_ACCESS_RDWR; in nouveau_channel_init()
337 args.start = 0; in nouveau_channel_init()
338 args.limit = mmu->limit - 1; in nouveau_channel_init()
342 &args, sizeof(args), &chan->gart); in nouveau_channel_init()