54 	int head;  in nv42_tv_sample_load()  local
62 	head = (dacclk & 0x100) >> 8;  in nv42_tv_sample_load()
67 	fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);  in nv42_tv_sample_load()
68 	fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);  in nv42_tv_sample_load()
69 	fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);  in nv42_tv_sample_load()
70 	fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);  in nv42_tv_sample_load()
72 	ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);  in nv42_tv_sample_load()
73 	ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);  in nv42_tv_sample_load()
74 	ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);  in nv42_tv_sample_load()
80 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);  in nv42_tv_sample_load()
81 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);  in nv42_tv_sample_load()
82 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183);  in nv42_tv_sample_load()
83 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,  in nv42_tv_sample_load()
98 	NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);  in nv42_tv_sample_load()
99 	NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);  in nv42_tv_sample_load()
102 	NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);  in nv42_tv_sample_load()
108 	NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);  in nv42_tv_sample_load()
114 	NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);  in nv42_tv_sample_load()
115 	NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);  in nv42_tv_sample_load()
116 	NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);  in nv42_tv_sample_load()
119 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);  in nv42_tv_sample_load()
120 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);  in nv42_tv_sample_load()
121 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);  in nv42_tv_sample_load()
122 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);  in nv42_tv_sample_load()
402 	int head = nouveau_crtc(encoder->crtc)->index;  in nv17_tv_prepare()  local
403 	uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[  in nv17_tv_prepare()
411 	nv04_dfp_disable(dev, head);  in nv17_tv_prepare()
418 		list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {  in nv17_tv_prepare()
424 			     nv04_dfp_get_bound_head(dev, dcb) == head) {  in nv17_tv_prepare()
425 				nv04_dfp_bind_head(dev, dcb, head ^ 1,  in nv17_tv_prepare()
433 		*cr_lcd |= 0x1 | (head ? 0x0 : 0x8);  in nv17_tv_prepare()
444 		if (head)  in nv17_tv_prepare()
463 	int head = nouveau_crtc(encoder->crtc)->index;  in nv17_tv_mode_set()  local
464 	struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];  in nv17_tv_mode_set()
477 		if (head)  in nv17_tv_mode_set()