Lines Matching refs:head
38 void NVWriteVgaSeq(struct drm_device *, int head, uint8_t index, uint8_t value);
39 uint8_t NVReadVgaSeq(struct drm_device *, int head, uint8_t index);
40 void NVWriteVgaGr(struct drm_device *, int head, uint8_t index, uint8_t value);
41 uint8_t NVReadVgaGr(struct drm_device *, int head, uint8_t index);
43 void NVBlankScreen(struct drm_device *, int head, bool blank);
49 void nouveau_hw_save_state(struct drm_device *, int head,
51 void nouveau_hw_load_state(struct drm_device *, int head,
53 void nouveau_hw_load_state_palette(struct drm_device *, int head,
61 int head, uint32_t reg) in NVReadCRTC() argument
65 if (head) in NVReadCRTC()
72 int head, uint32_t reg, uint32_t val) in NVWriteCRTC() argument
75 if (head) in NVWriteCRTC()
81 int head, uint32_t reg) in NVReadRAMDAC() argument
85 if (head) in NVReadRAMDAC()
92 int head, uint32_t reg, uint32_t val) in NVWriteRAMDAC() argument
95 if (head) in NVWriteRAMDAC()
121 int head, uint8_t index, uint8_t value) in NVWriteVgaCrtc() argument
124 nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index); in NVWriteVgaCrtc()
125 nvif_wr08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value); in NVWriteVgaCrtc()
129 int head, uint8_t index) in NVReadVgaCrtc() argument
133 nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index); in NVReadVgaCrtc()
134 val = nvif_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE); in NVReadVgaCrtc()
153 NVWriteVgaCrtc5758(struct drm_device *dev, int head, uint8_t index, uint8_t value) in NVWriteVgaCrtc5758() argument
155 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index); in NVWriteVgaCrtc5758()
156 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_58, value); in NVWriteVgaCrtc5758()
159 static inline uint8_t NVReadVgaCrtc5758(struct drm_device *dev, int head, uint8_t index) in NVReadVgaCrtc5758() argument
161 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index); in NVReadVgaCrtc5758()
162 return NVReadVgaCrtc(dev, head, NV_CIO_CRE_58); in NVReadVgaCrtc5758()
166 int head, uint32_t reg) in NVReadPRMVIO() argument
174 if (head && drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) in NVReadPRMVIO()
182 int head, uint32_t reg, uint8_t value) in NVWritePRMVIO() argument
189 if (head && drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) in NVWritePRMVIO()
195 static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable) in NVSetEnablePalette() argument
198 nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE); in NVSetEnablePalette()
199 nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20); in NVSetEnablePalette()
202 static inline bool NVGetEnablePalette(struct drm_device *dev, int head) in NVGetEnablePalette() argument
205 nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE); in NVGetEnablePalette()
206 return !(nvif_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20); in NVGetEnablePalette()
210 int head, uint8_t index, uint8_t value) in NVWriteVgaAttr() argument
213 if (NVGetEnablePalette(dev, head)) in NVWriteVgaAttr()
218 nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE); in NVWriteVgaAttr()
219 nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index); in NVWriteVgaAttr()
220 nvif_wr08(device, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value); in NVWriteVgaAttr()
224 int head, uint8_t index) in NVReadVgaAttr() argument
228 if (NVGetEnablePalette(dev, head)) in NVReadVgaAttr()
233 nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE); in NVReadVgaAttr()
234 nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index); in NVReadVgaAttr()
235 val = nvif_rd08(device, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE); in NVReadVgaAttr()
239 static inline void NVVgaSeqReset(struct drm_device *dev, int head, bool start) in NVVgaSeqReset() argument
241 NVWriteVgaSeq(dev, head, NV_VIO_SR_RESET_INDEX, start ? 0x1 : 0x3); in NVVgaSeqReset()
244 static inline void NVVgaProtect(struct drm_device *dev, int head, bool protect) in NVVgaProtect() argument
246 uint8_t seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); in NVVgaProtect()
249 NVVgaSeqReset(dev, head, true); in NVVgaProtect()
250 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); in NVVgaProtect()
253 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); /* reenable display */ in NVVgaProtect()
254 NVVgaSeqReset(dev, head, false); in NVVgaProtect()
256 NVSetEnablePalette(dev, head, protect); in NVVgaProtect()
273 nv_lock_vga_crtc_base(struct drm_device *dev, int head, bool lock) in nv_lock_vga_crtc_base() argument
275 uint8_t cr11 = NVReadVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX); in nv_lock_vga_crtc_base()
282 NVWriteVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX, cr11); in nv_lock_vga_crtc_base()
288 nv_lock_vga_crtc_shadow(struct drm_device *dev, int head, int lock) in nv_lock_vga_crtc_shadow() argument
304 cr21 = NVReadVgaCrtc(dev, head, NV_CIO_CRE_21) | 0xfa; in nv_lock_vga_crtc_shadow()
306 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_21, cr21); in nv_lock_vga_crtc_shadow()
342 nv_fix_nv40_hw_cursor(struct drm_device *dev, int head) in nv_fix_nv40_hw_cursor() argument
349 uint32_t curpos = NVReadRAMDAC(dev, head, NV_PRAMDAC_CU_START_POS); in nv_fix_nv40_hw_cursor()
350 NVWriteRAMDAC(dev, head, NV_PRAMDAC_CU_START_POS, curpos); in nv_fix_nv40_hw_cursor()
354 nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset) in nv_set_crtc_base() argument
358 NVWriteCRTC(dev, head, NV_PCRTC_START, offset); in nv_set_crtc_base()
365 int cre_heb = NVReadVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX); in nv_set_crtc_base()
367 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX, in nv_set_crtc_base()
373 nv_show_cursor(struct drm_device *dev, int head, bool show) in nv_show_cursor() argument
377 &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]; in nv_show_cursor()
383 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1); in nv_show_cursor()
386 nv_fix_nv40_hw_cursor(dev, head); in nv_show_cursor()