373 rd_cio_state(struct drm_device *dev, int head,  in rd_cio_state()  function
543 		rd_cio_state(dev, head, regp, i);  in nv_save_state_vga()
591 	rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);  in nv_save_state_ext()
592 	rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);  in nv_save_state_ext()
593 	rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);  in nv_save_state_ext()
594 	rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);  in nv_save_state_ext()
595 	rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);  in nv_save_state_ext()
596 	rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);  in nv_save_state_ext()
597 	rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);  in nv_save_state_ext()
599 	rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);  in nv_save_state_ext()
600 	rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);  in nv_save_state_ext()
601 	rd_cio_state(dev, head, regp, NV_CIO_CRE_21);  in nv_save_state_ext()
604 		rd_cio_state(dev, head, regp, NV_CIO_CRE_47);  in nv_save_state_ext()
607 		rd_cio_state(dev, head, regp, 0x9f);  in nv_save_state_ext()
609 	rd_cio_state(dev, head, regp, NV_CIO_CRE_49);  in nv_save_state_ext()
610 	rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);  in nv_save_state_ext()
611 	rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);  in nv_save_state_ext()
612 	rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);  in nv_save_state_ext()
613 	rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);  in nv_save_state_ext()
632 	rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);  in nv_save_state_ext()
633 	rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);  in nv_save_state_ext()
635 		rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);  in nv_save_state_ext()
636 		rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);  in nv_save_state_ext()
637 		rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);  in nv_save_state_ext()
638 		rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);  in nv_save_state_ext()
642 		rd_cio_state(dev, head, regp, NV_CIO_CRE_42);  in nv_save_state_ext()
643 		rd_cio_state(dev, head, regp, NV_CIO_CRE_53);  in nv_save_state_ext()
644 		rd_cio_state(dev, head, regp, NV_CIO_CRE_54);  in nv_save_state_ext()
648 		rd_cio_state(dev, head, regp, NV_CIO_CRE_59);  in nv_save_state_ext()
649 		rd_cio_state(dev, head, regp, NV_CIO_CRE_5B);  in nv_save_state_ext()
651 		rd_cio_state(dev, head, regp, NV_CIO_CRE_85);  in nv_save_state_ext()
652 		rd_cio_state(dev, head, regp, NV_CIO_CRE_86);  in nv_save_state_ext()