Lines Matching refs:nv_crtc
59 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_set_digital_vibrance() local
61 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_digital_vibrance()
63 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; in nv_crtc_set_digital_vibrance()
64 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { in nv_crtc_set_digital_vibrance()
66 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; in nv_crtc_set_digital_vibrance()
74 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_set_image_sharpening() local
76 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_image_sharpening()
78 nv_crtc->sharpness = level; in nv_crtc_set_image_sharpening()
82 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); in nv_crtc_set_image_sharpening()
117 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_calc_state_ext() local
119 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; in nv_crtc_calc_state_ext()
123 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, in nv_crtc_calc_state_ext()
156 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; in nv_crtc_calc_state_ext()
165 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); in nv_crtc_calc_state_ext()
171 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_dpms() local
178 nv_crtc->index); in nv_crtc_dpms()
180 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */ in nv_crtc_dpms()
183 nv_crtc->last_dpms = mode; in nv_crtc_dpms()
186 NVSetOwner(dev, nv_crtc->index); in nv_crtc_dpms()
189 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index, in nv_crtc_dpms()
218 NVVgaSeqReset(dev, nv_crtc->index, true); in nv_crtc_dpms()
220 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); in nv_crtc_dpms()
221 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); in nv_crtc_dpms()
222 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80); in nv_crtc_dpms()
224 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); in nv_crtc_dpms()
225 NVVgaSeqReset(dev, nv_crtc->index, false); in nv_crtc_dpms()
227 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); in nv_crtc_dpms()
241 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_mode_set_vga() local
242 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_vga()
466 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_mode_set_regs() local
467 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_regs()
468 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_regs()
498 if (nv_crtc->index == 0) in nv_crtc_mode_set_regs()
504 if (pPriv->overlayCRTC == nv_crtc->index) in nv_crtc_mode_set_regs()
534 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); in nv_crtc_mode_set_regs()
541 if (nv_crtc->index == 0) in nv_crtc_mode_set_regs()
547 if (!nv_crtc->index) in nv_crtc_mode_set_regs()
600 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); in nv_crtc_mode_set_regs()
614 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_swap_fbs() local
619 if (disp->image[nv_crtc->index]) in nv_crtc_swap_fbs()
620 nouveau_bo_unpin(disp->image[nv_crtc->index]); in nv_crtc_swap_fbs()
621 nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]); in nv_crtc_swap_fbs()
641 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_mode_set() local
645 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index); in nv_crtc_mode_set()
653 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1); in nv_crtc_mode_set()
666 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_save() local
669 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; in nv_crtc_save()
671 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index]; in nv_crtc_save()
674 NVSetOwner(crtc->dev, nv_crtc->index); in nv_crtc_save()
676 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); in nv_crtc_save()
687 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_restore() local
689 int head = nv_crtc->index; in nv_crtc_restore()
698 nv_crtc->last_dpms = NV_DPMS_CLEARED; in nv_crtc_restore()
705 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_prepare() local
709 NVSetOwner(dev, nv_crtc->index); in nv_crtc_prepare()
711 drm_vblank_pre_modeset(dev, nv_crtc->index); in nv_crtc_prepare()
714 NVBlankScreen(dev, nv_crtc->index, true); in nv_crtc_prepare()
717 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); in nv_crtc_prepare()
719 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); in nv_crtc_prepare()
720 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); in nv_crtc_prepare()
728 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_commit() local
730 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); in nv_crtc_commit()
736 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR); in nv_crtc_commit()
738 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); in nv_crtc_commit()
743 drm_vblank_post_modeset(dev, nv_crtc->index); in nv_crtc_commit()
749 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_destroy() local
751 if (!nv_crtc) in nv_crtc_destroy()
756 if (disp->image[nv_crtc->index]) in nv_crtc_destroy()
757 nouveau_bo_unpin(disp->image[nv_crtc->index]); in nv_crtc_destroy()
758 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); in nv_crtc_destroy()
760 nouveau_bo_unmap(nv_crtc->cursor.nvbo); in nv_crtc_destroy()
761 nouveau_bo_unpin(nv_crtc->cursor.nvbo); in nv_crtc_destroy()
762 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); in nv_crtc_destroy()
763 kfree(nv_crtc); in nv_crtc_destroy()
769 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_gamma_load() local
770 struct drm_device *dev = nv_crtc->base.dev; in nv_crtc_gamma_load()
774 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; in nv_crtc_gamma_load()
776 rgbs[i].r = nv_crtc->lut.r[i] >> 8; in nv_crtc_gamma_load()
777 rgbs[i].g = nv_crtc->lut.g[i] >> 8; in nv_crtc_gamma_load()
778 rgbs[i].b = nv_crtc->lut.b[i] >> 8; in nv_crtc_gamma_load()
781 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); in nv_crtc_gamma_load()
788 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_disable() local
789 if (disp->image[nv_crtc->index]) in nv_crtc_disable()
790 nouveau_bo_unpin(disp->image[nv_crtc->index]); in nv_crtc_disable()
791 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); in nv_crtc_disable()
799 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_gamma_set() local
802 nv_crtc->lut.r[i] = r[i]; in nv_crtc_gamma_set()
803 nv_crtc->lut.g[i] = g[i]; in nv_crtc_gamma_set()
804 nv_crtc->lut.b[i] = b[i]; in nv_crtc_gamma_set()
812 if (!nv_crtc->base.primary->fb) { in nv_crtc_gamma_set()
813 nv_crtc->lut.depth = 0; in nv_crtc_gamma_set()
825 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv04_crtc_do_mode_set_base() local
828 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_crtc_do_mode_set_base()
833 NV_DEBUG(drm, "index %d\n", nv_crtc->index); in nv04_crtc_do_mode_set_base()
852 nv_crtc->fb.offset = fb->nvbo->bo.offset; in nv04_crtc_do_mode_set_base()
854 if (nv_crtc->lut.depth != drm_fb->depth) { in nv04_crtc_do_mode_set_base()
855 nv_crtc->lut.depth = drm_fb->depth; in nv04_crtc_do_mode_set_base()
866 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, in nv04_crtc_do_mode_set_base()
879 regp->fb_start = nv_crtc->fb.offset & ~3; in nv04_crtc_do_mode_set_base()
881 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); in nv04_crtc_do_mode_set_base()
992 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv04_crtc_cursor_set() local
998 nv_crtc->cursor.hide(nv_crtc, true); in nv04_crtc_cursor_set()
1015 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); in nv04_crtc_cursor_set()
1017 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); in nv04_crtc_cursor_set()
1020 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset; in nv04_crtc_cursor_set()
1021 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); in nv04_crtc_cursor_set()
1022 nv_crtc->cursor.show(nv_crtc, true); in nv04_crtc_cursor_set()
1031 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv04_crtc_cursor_move() local
1033 nv_crtc->cursor.set_pos(nv_crtc, x, y); in nv04_crtc_cursor_move()
1109 struct nouveau_crtc *nv_crtc; in nv04_crtc_create() local
1112 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); in nv04_crtc_create()
1113 if (!nv_crtc) in nv04_crtc_create()
1117 nv_crtc->lut.r[i] = i << 8; in nv04_crtc_create()
1118 nv_crtc->lut.g[i] = i << 8; in nv04_crtc_create()
1119 nv_crtc->lut.b[i] = i << 8; in nv04_crtc_create()
1121 nv_crtc->lut.depth = 0; in nv04_crtc_create()
1123 nv_crtc->index = crtc_num; in nv04_crtc_create()
1124 nv_crtc->last_dpms = NV_DPMS_CLEARED; in nv04_crtc_create()
1126 drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs); in nv04_crtc_create()
1127 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); in nv04_crtc_create()
1128 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); in nv04_crtc_create()
1131 0, 0x0000, NULL, NULL, &nv_crtc->cursor.nvbo); in nv04_crtc_create()
1133 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM, false); in nv04_crtc_create()
1135 ret = nouveau_bo_map(nv_crtc->cursor.nvbo); in nv04_crtc_create()
1137 nouveau_bo_unpin(nv_crtc->cursor.nvbo); in nv04_crtc_create()
1140 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); in nv04_crtc_create()
1143 nv04_cursor_init(nv_crtc); in nv04_crtc_create()