51 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)  in crtc_wr_cio_state()  argument
53 	NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,  in crtc_wr_cio_state()
54 		       crtcstate->CRTC[index]);  in crtc_wr_cio_state()
61 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];  in nv_crtc_set_digital_vibrance()
76 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];  in nv_crtc_set_image_sharpening()
82 	NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634);  in nv_crtc_set_image_sharpening()
119 	struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];  in nv_crtc_calc_state_ext()
123 	if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0,  in nv_crtc_calc_state_ext()
156 	state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;  in nv_crtc_calc_state_ext()
178 							nv_crtc->index);  in nv_crtc_dpms()
186 		NVSetOwner(dev, nv_crtc->index);  in nv_crtc_dpms()
189 	crtc1A = NVReadVgaCrtc(dev, nv_crtc->index,  in nv_crtc_dpms()
218 	NVVgaSeqReset(dev, nv_crtc->index, true);  in nv_crtc_dpms()
220 	seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20);  in nv_crtc_dpms()
221 	NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);  in nv_crtc_dpms()
222 	crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80);  in nv_crtc_dpms()
224 	NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17);  in nv_crtc_dpms()
225 	NVVgaSeqReset(dev, nv_crtc->index, false);  in nv_crtc_dpms()
227 	NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A);  in nv_crtc_dpms()
242 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];  in nv_crtc_mode_set_vga()
467 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];  in nv_crtc_mode_set_regs()
468 	struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];  in nv_crtc_mode_set_regs()
498 	if (nv_crtc->index == 0)  in nv_crtc_mode_set_regs()
504 		if (pPriv->overlayCRTC == nv_crtc->index)  in nv_crtc_mode_set_regs()
541 	if (nv_crtc->index == 0)  in nv_crtc_mode_set_regs()
547 	if (!nv_crtc->index)  in nv_crtc_mode_set_regs()
619 		if (disp->image[nv_crtc->index])  in nv_crtc_swap_fbs()
620 			nouveau_bo_unpin(disp->image[nv_crtc->index]);  in nv_crtc_swap_fbs()
621 		nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]);  in nv_crtc_swap_fbs()
645 	NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index);  in nv_crtc_mode_set()
653 	nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1);  in nv_crtc_mode_set()
669 	struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index];  in nv_crtc_save()
671 	struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index];  in nv_crtc_save()
674 		NVSetOwner(crtc->dev, nv_crtc->index);  in nv_crtc_save()
676 	nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved);  in nv_crtc_save()
689 	int head = nv_crtc->index;  in nv_crtc_restore()
709 		NVSetOwner(dev, nv_crtc->index);  in nv_crtc_prepare()
711 	drm_vblank_pre_modeset(dev, nv_crtc->index);  in nv_crtc_prepare()
714 	NVBlankScreen(dev, nv_crtc->index, true);  in nv_crtc_prepare()
717 	NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);  in nv_crtc_prepare()
719 		uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);  in nv_crtc_prepare()
720 		NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);  in nv_crtc_prepare()
730 	nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);  in nv_crtc_commit()
736 		uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR);  in nv_crtc_commit()
738 		NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp);  in nv_crtc_commit()
743 	drm_vblank_post_modeset(dev, nv_crtc->index);  in nv_crtc_commit()
756 	if (disp->image[nv_crtc->index])  in nv_crtc_destroy()
757 		nouveau_bo_unpin(disp->image[nv_crtc->index]);  in nv_crtc_destroy()
758 	nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);  in nv_crtc_destroy()
774 	rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC;  in nv_crtc_gamma_load()
781 	nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);  in nv_crtc_gamma_load()
789 	if (disp->image[nv_crtc->index])  in nv_crtc_disable()
790 		nouveau_bo_unpin(disp->image[nv_crtc->index]);  in nv_crtc_disable()
791 	nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);  in nv_crtc_disable()
828 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];  in nv04_crtc_do_mode_set_base()
833 	NV_DEBUG(drm, "index %d\n", nv_crtc->index);  in nv04_crtc_do_mode_set_base()
866 	NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL,  in nv04_crtc_do_mode_set_base()
881 	nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start);  in nv04_crtc_do_mode_set_base()
1123 	nv_crtc->index = crtc_num;  in nv04_crtc_create()