116 	u32 pixel_rate; /* in kHz */  member
247 				(unsigned long)ctrl->pixel_rate * 1000);  in edp_clk_enable()
249 				(unsigned long)ctrl->pixel_rate * 1000);  in edp_clk_enable()
422 	prate = ctrl->pixel_rate;  in edp_fill_link_cfg()
720 	prate = ctrl->pixel_rate;  in edp_link_rate_down_shift()
740 			ctrl->pixel_rate,  in edp_link_rate_down_shift()
924 		msm_edp_ctrl_pixel_clock_valid(ctrl, ctrl->pixel_rate, &m, &n);  in edp_ctrl_link_enable()
1283 	ctrl->pixel_rate = mode->clock;  in msm_edp_ctrl_timing_cfg()
1329 	u32 pixel_rate, u32 *pm, u32 *pn)  in msm_edp_ctrl_pixel_clock_valid()  argument
1346 		clk_err = abs(divs[i].rate - pixel_rate);  in msm_edp_ctrl_pixel_clock_valid()
1356 	DBG("pixel clock %d(kHz) not supported", pixel_rate);  in msm_edp_ctrl_pixel_clock_valid()