145 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,  in msm_dsi_phy_set_src_pll()  argument
148 	int phy_id = phy->id;  in msm_dsi_phy_set_src_pll()
154 	val = dsi_phy_read(phy->base + reg);  in msm_dsi_phy_set_src_pll()
156 	if (phy->cfg->src_pll_truthtable[phy_id][pll_id])  in msm_dsi_phy_set_src_pll()
157 		dsi_phy_write(phy->base + reg, val | bit_mask);  in msm_dsi_phy_set_src_pll()
159 		dsi_phy_write(phy->base + reg, val & (~bit_mask));  in msm_dsi_phy_set_src_pll()
162 static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)  in dsi_phy_regulator_init()  argument
164 	struct regulator_bulk_data *s = phy->supplies;  in dsi_phy_regulator_init()
165 	const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;  in dsi_phy_regulator_init()
166 	struct device *dev = &phy->pdev->dev;  in dsi_phy_regulator_init()
167 	int num = phy->cfg->reg_cfg.num;  in dsi_phy_regulator_init()
196 static void dsi_phy_regulator_disable(struct msm_dsi_phy *phy)  in dsi_phy_regulator_disable()  argument
198 	struct regulator_bulk_data *s = phy->supplies;  in dsi_phy_regulator_disable()
199 	const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;  in dsi_phy_regulator_disable()
200 	int num = phy->cfg->reg_cfg.num;  in dsi_phy_regulator_disable()
211 static int dsi_phy_regulator_enable(struct msm_dsi_phy *phy)  in dsi_phy_regulator_enable()  argument
213 	struct regulator_bulk_data *s = phy->supplies;  in dsi_phy_regulator_enable()
214 	const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;  in dsi_phy_regulator_enable()
215 	struct device *dev = &phy->pdev->dev;  in dsi_phy_regulator_enable()
216 	int num = phy->cfg->reg_cfg.num;  in dsi_phy_regulator_enable()
247 static int dsi_phy_enable_resource(struct msm_dsi_phy *phy)  in dsi_phy_enable_resource()  argument
249 	struct device *dev = &phy->pdev->dev;  in dsi_phy_enable_resource()
254 	ret = clk_prepare_enable(phy->ahb_clk);  in dsi_phy_enable_resource()
263 static void dsi_phy_disable_resource(struct msm_dsi_phy *phy)  in dsi_phy_disable_resource()  argument
265 	clk_disable_unprepare(phy->ahb_clk);  in dsi_phy_disable_resource()
266 	pm_runtime_put_sync(&phy->pdev->dev);  in dsi_phy_disable_resource()
285 	struct msm_dsi_phy *phy;  in dsi_phy_driver_probe()  local
290 	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);  in dsi_phy_driver_probe()
291 	if (!phy)  in dsi_phy_driver_probe()
298 	phy->cfg = match->data;  in dsi_phy_driver_probe()
299 	phy->pdev = pdev;  in dsi_phy_driver_probe()
302 				"qcom,dsi-phy-index", &phy->id);  in dsi_phy_driver_probe()
309 	phy->regulator_ldo_mode = of_property_read_bool(dev->of_node,  in dsi_phy_driver_probe()
312 	phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");  in dsi_phy_driver_probe()
313 	if (IS_ERR(phy->base)) {  in dsi_phy_driver_probe()
319 	phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",  in dsi_phy_driver_probe()
321 	if (IS_ERR(phy->reg_base)) {  in dsi_phy_driver_probe()
328 	ret = dsi_phy_regulator_init(phy);  in dsi_phy_driver_probe()
334 	phy->ahb_clk = devm_clk_get(dev, "iface_clk");  in dsi_phy_driver_probe()
335 	if (IS_ERR(phy->ahb_clk)) {  in dsi_phy_driver_probe()
337 		ret = PTR_ERR(phy->ahb_clk);  in dsi_phy_driver_probe()
344 	ret = dsi_phy_enable_resource(phy);  in dsi_phy_driver_probe()
348 	phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id);  in dsi_phy_driver_probe()
349 	if (!phy->pll)  in dsi_phy_driver_probe()
354 	dsi_phy_disable_resource(phy);  in dsi_phy_driver_probe()
356 	platform_set_drvdata(pdev, phy);  in dsi_phy_driver_probe()
366 	struct msm_dsi_phy *phy = platform_get_drvdata(pdev);  in dsi_phy_driver_remove()  local
368 	if (phy && phy->pll) {  in dsi_phy_driver_remove()
369 		msm_dsi_pll_destroy(phy->pll);  in dsi_phy_driver_remove()
370 		phy->pll = NULL;  in dsi_phy_driver_remove()
397 int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,  in msm_dsi_phy_enable()  argument
400 	struct device *dev = &phy->pdev->dev;  in msm_dsi_phy_enable()
403 	if (!phy || !phy->cfg->ops.enable)  in msm_dsi_phy_enable()
406 	ret = dsi_phy_regulator_enable(phy);  in msm_dsi_phy_enable()
413 	ret = phy->cfg->ops.enable(phy, src_pll_id, bit_rate, esc_rate);  in msm_dsi_phy_enable()
416 		dsi_phy_regulator_disable(phy);  in msm_dsi_phy_enable()
423 void msm_dsi_phy_disable(struct msm_dsi_phy *phy)  in msm_dsi_phy_disable()  argument
425 	if (!phy || !phy->cfg->ops.disable)  in msm_dsi_phy_disable()
428 	phy->cfg->ops.disable(phy);  in msm_dsi_phy_disable()
430 	dsi_phy_regulator_disable(phy);  in msm_dsi_phy_disable()
433 void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy,  in msm_dsi_phy_get_clk_pre_post()  argument
436 	if (!phy)  in msm_dsi_phy_get_clk_pre_post()
440 		*clk_pre = phy->timing.clk_pre;  in msm_dsi_phy_get_clk_pre_post()
442 		*clk_post = phy->timing.clk_post;  in msm_dsi_phy_get_clk_pre_post()
445 struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy)  in msm_dsi_phy_get_pll()  argument
447 	if (!phy)  in msm_dsi_phy_get_pll()
450 	return phy->pll;  in msm_dsi_phy_get_pll()