174 		pr_err("%s: cannot get gdsc\n", __func__);  in dsi_get_config()
179 		pr_err("%s: unable to enable gdsc\n", __func__);  in dsi_get_config()
184 		pr_err("%s: unable to enable ahb_clk\n", __func__);  in dsi_get_config()
190 		pr_err("%s: Invalid version\n", __func__);  in dsi_get_config()
242 				pr_err("regulator %d set op mode failed, %d\n",  in dsi_host_regulator_enable()
251 		pr_err("regulator enable failed, %d\n", ret);  in dsi_host_regulator_enable()
275 		pr_err("%s: failed to init regulator, ret=%d\n",  in dsi_regulator_init()
285 				pr_err("regulator %d set voltage failed, %d\n",  in dsi_regulator_init()
303 		pr_err("%s: Unable to get mdp core clk. ret=%d\n",  in dsi_clk_init()
311 		pr_err("%s: Unable to get mdss ahb clk. ret=%d\n",  in dsi_clk_init()
319 		pr_err("%s: Unable to get axi bus clk. ret=%d\n",  in dsi_clk_init()
327 		pr_err("%s: Unable to get mmss misc ahb clk. ret=%d\n",  in dsi_clk_init()
335 		pr_err("%s: can't find dsi_byte_clk. ret=%d\n",  in dsi_clk_init()
344 		pr_err("%s: can't find dsi_pixel_clk. ret=%d\n",  in dsi_clk_init()
353 		pr_err("%s: can't find dsi_esc_clk. ret=%d\n",  in dsi_clk_init()
362 		pr_err("%s: can't find byte_clk_src. ret=%d\n", __func__, ret);  in dsi_clk_init()
370 		pr_err("%s: can't find pixel_clk_src. ret=%d\n", __func__, ret);  in dsi_clk_init()
387 		pr_err("%s: failed to enable mdp_core_clock, %d\n",  in dsi_bus_clk_enable()
394 		pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret);  in dsi_bus_clk_enable()
400 		pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret);  in dsi_bus_clk_enable()
406 		pr_err("%s: failed to enable mmss misc ahb clk, %d\n",  in dsi_bus_clk_enable()
441 		pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);  in dsi_link_clk_enable()
447 		pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);  in dsi_link_clk_enable()
453 		pr_err("%s: Failed to enable dsi esc clk\n", __func__);  in dsi_link_clk_enable()
459 		pr_err("%s: Failed to enable dsi byte clk\n", __func__);  in dsi_link_clk_enable()
465 		pr_err("%s: Failed to enable dsi pixel clk\n", __func__);  in dsi_link_clk_enable()
494 			pr_err("%s: Can not enable bus clk, %d\n",  in dsi_clk_ctrl()
500 			pr_err("%s: Can not enable link clk, %d\n",  in dsi_clk_ctrl()
523 		pr_err("%s: mode not set\n", __func__);  in dsi_calc_clk_rate()
531 		pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);  in dsi_calc_clk_rate()
845 		pr_err("%s: failed to allocate gem, %d\n", __func__, ret);  in dsi_tx_buf_alloc()
853 		pr_err("%s: failed to get iova, %d\n", __func__, ret);  in dsi_tx_buf_alloc()
859 		pr_err("%s: buf NOT 8 bytes aligned\n", __func__);  in dsi_tx_buf_alloc()
892 		pr_err("%s: create packet failed, %d\n", __func__, ret);  in dsi_cmd_dma_add()
898 		pr_err("%s: packet size is too big\n", __func__);  in dsi_cmd_dma_add()
906 		pr_err("%s: get vaddr failed, %d\n", __func__, ret);  in dsi_cmd_dma_add()
941 		pr_err("%s: read data does not match with rx_buf len %zu\n",  in dsi_short_read1_resp()
958 		pr_err("%s: read data does not match with rx_buf len %zu\n",  in dsi_short_read2_resp()
982 		pr_err("%s: failed to get iova: %d\n", __func__, ret);  in dsi_cmd_dma_tx()
1065 		pr_err("%s: failed to add cmd type = 0x%x\n",  in dsi_cmds2buf_tx()
1080 		pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",  in dsi_cmds2buf_tx()
1087 		pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n",  in dsi_cmds2buf_tx()
1397 		pr_err("%s: FAILED: cannot alloc dsi host\n",  in msm_dsi_host_init()
1407 		pr_err("%s: failed to parse dt\n", __func__);  in msm_dsi_host_init()
1413 		pr_err("%s: unable to initialize dsi clks\n", __func__);  in msm_dsi_host_init()
1419 		pr_err("%s: unable to map Dsi ctrl base\n", __func__);  in msm_dsi_host_init()
1427 		pr_err("%s: get config failed\n", __func__);  in msm_dsi_host_init()
1436 		pr_err("%s: regulator init failed\n", __func__);  in msm_dsi_host_init()
1442 		pr_err("%s: alloc rx temp buf failed\n", __func__);  in msm_dsi_host_init()
1510 		pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);  in msm_dsi_host_modeset_init()
1659 			pr_err("%s: Set max pkt size failed, %d\n",  in msm_dsi_host_cmd_rx()
1676 			pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);  in msm_dsi_host_cmd_rx()
1730 		pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);  in msm_dsi_host_cmd_rx()
1782 		pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",  in msm_dsi_host_set_src_pll()
1789 		pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",  in msm_dsi_host_set_src_pll()
1845 		pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);  in msm_dsi_host_power_on()
1851 		pr_err("%s:Failed to enable vregs.ret=%d\n",  in msm_dsi_host_power_on()
1858 		pr_err("%s: failed to enable bus clocks, %d\n", __func__, ret);  in msm_dsi_host_power_on()
1869 		pr_err("%s: failed to enable phy, %d\n", __func__, ret);  in msm_dsi_host_power_on()
1875 		pr_err("%s: failed to enable clocks. ret=%d\n", __func__, ret);  in msm_dsi_host_power_on()
1881 		pr_err("%s: failed to set pinctrl default state, %d\n",  in msm_dsi_host_power_on()
1951 		pr_err("%s: cannot duplicate mode\n", __func__);  in msm_dsi_host_set_display_mode()