156 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)  in dsi_write()  function
543 	dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);  in dsi_phy_sw_reset()
547 	dsi_write(msm_host, REG_DSI_PHY_RESET, 0);  in dsi_phy_sw_reset()
566 	dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);  in dsi_intr_ctrl()
613 		dsi_write(msm_host, REG_DSI_CTRL, 0);  in dsi_ctrl_config()
634 		dsi_write(msm_host, REG_DSI_VID_CFG0, data);  in dsi_ctrl_config()
638 		dsi_write(msm_host, REG_DSI_VID_CFG1, 0);  in dsi_ctrl_config()
643 		dsi_write(msm_host, REG_DSI_CMD_CFG0, data);  in dsi_ctrl_config()
650 		dsi_write(msm_host, REG_DSI_CMD_CFG1, data);  in dsi_ctrl_config()
653 	dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,  in dsi_ctrl_config()
666 	dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);  in dsi_ctrl_config()
670 	dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);  in dsi_ctrl_config()
675 	dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);  in dsi_ctrl_config()
678 	dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);  in dsi_ctrl_config()
682 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);  in dsi_ctrl_config()
690 		dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,  in dsi_ctrl_config()
697 		dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,  in dsi_ctrl_config()
702 		dsi_write(msm_host, REG_DSI_LANE_CTRL,  in dsi_ctrl_config()
707 	dsi_write(msm_host, REG_DSI_CTRL, data);  in dsi_ctrl_config()
727 		dsi_write(msm_host, REG_DSI_ACTIVE_H,  in dsi_timing_setup()
730 		dsi_write(msm_host, REG_DSI_ACTIVE_V,  in dsi_timing_setup()
733 		dsi_write(msm_host, REG_DSI_TOTAL,  in dsi_timing_setup()
737 		dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,  in dsi_timing_setup()
740 		dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);  in dsi_timing_setup()
741 		dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,  in dsi_timing_setup()
748 		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,  in dsi_timing_setup()
755 		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,  in dsi_timing_setup()
763 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);  in dsi_sw_reset()
766 	dsi_write(msm_host, REG_DSI_RESET, 1);  in dsi_sw_reset()
768 	dsi_write(msm_host, REG_DSI_RESET, 0);  in dsi_sw_reset()
793 	dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);  in dsi_op_mode_config()
807 	dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);  in dsi_set_tx_power_mode()
1102 	dsi_write(msm_host, REG_DSI_CTRL, data1);  in dsi_sw_reset_restore()
1109 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);  in dsi_sw_reset_restore()
1113 	dsi_write(msm_host, REG_DSI_RESET, 1);  in dsi_sw_reset_restore()
1115 	dsi_write(msm_host, REG_DSI_RESET, 0);  in dsi_sw_reset_restore()
1117 	dsi_write(msm_host, REG_DSI_CTRL, data0);  in dsi_sw_reset_restore()
1145 		dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);  in dsi_ack_err_status()
1147 		dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);  in dsi_ack_err_status()
1159 		dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);  in dsi_timeout_status()
1175 		dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);  in dsi_dln0_phy_err()
1188 		dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);  in dsi_fifo_status()
1203 		dsi_write(msm_host, REG_DSI_STATUS0, status);  in dsi_status()
1216 		dsi_write(msm_host, REG_DSI_CLK_STATUS, status);  in dsi_clk_status()
1247 	dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);  in dsi_host_irq()
1585 	dsi_write(msm_host, REG_DSI_CTRL,  in msm_dsi_host_xfer_prepare()
1600 	dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);  in msm_dsi_host_xfer_restore()
1667 			dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,  in msm_dsi_host_cmd_rx()
1670 			dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);  in msm_dsi_host_cmd_rx()
1757 	dsi_write(msm_host, REG_DSI_DMA_BASE, iova);  in msm_dsi_host_cmd_xfer_commit()
1758 	dsi_write(msm_host, REG_DSI_DMA_LEN, len);  in msm_dsi_host_cmd_xfer_commit()
1759 	dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);  in msm_dsi_host_cmd_xfer_commit()