Lines Matching refs:val
112 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) in DSI_6G_HW_VERSION_MAJOR() argument
114 return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; in DSI_6G_HW_VERSION_MAJOR()
118 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) in DSI_6G_HW_VERSION_MINOR() argument
120 return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; in DSI_6G_HW_VERSION_MINOR()
124 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) in DSI_6G_HW_VERSION_STEP() argument
126 return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; in DSI_6G_HW_VERSION_STEP()
155 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) in DSI_VID_CFG0_VIRT_CHANNEL() argument
157 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; in DSI_VID_CFG0_VIRT_CHANNEL()
161 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) in DSI_VID_CFG0_DST_FORMAT() argument
163 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; in DSI_VID_CFG0_DST_FORMAT()
167 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) in DSI_VID_CFG0_TRAFFIC_MODE() argument
169 return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK; in DSI_VID_CFG0_TRAFFIC_MODE()
184 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) in DSI_VID_CFG1_RGB_SWAP() argument
186 return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK; in DSI_VID_CFG1_RGB_SWAP()
192 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) in DSI_ACTIVE_H_START() argument
194 return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK; in DSI_ACTIVE_H_START()
198 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) in DSI_ACTIVE_H_END() argument
200 return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK; in DSI_ACTIVE_H_END()
206 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) in DSI_ACTIVE_V_START() argument
208 return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK; in DSI_ACTIVE_V_START()
212 static inline uint32_t DSI_ACTIVE_V_END(uint32_t val) in DSI_ACTIVE_V_END() argument
214 return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK; in DSI_ACTIVE_V_END()
220 static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val) in DSI_TOTAL_H_TOTAL() argument
222 return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK; in DSI_TOTAL_H_TOTAL()
226 static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val) in DSI_TOTAL_V_TOTAL() argument
228 return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK; in DSI_TOTAL_V_TOTAL()
234 static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val) in DSI_ACTIVE_HSYNC_START() argument
236 return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK; in DSI_ACTIVE_HSYNC_START()
240 static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val) in DSI_ACTIVE_HSYNC_END() argument
242 return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK; in DSI_ACTIVE_HSYNC_END()
248 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val) in DSI_ACTIVE_VSYNC_HPOS_START() argument
250 return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK; in DSI_ACTIVE_VSYNC_HPOS_START()
254 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val) in DSI_ACTIVE_VSYNC_HPOS_END() argument
256 return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK; in DSI_ACTIVE_VSYNC_HPOS_END()
262 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val) in DSI_ACTIVE_VSYNC_VPOS_START() argument
264 return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK; in DSI_ACTIVE_VSYNC_VPOS_START()
268 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val) in DSI_ACTIVE_VSYNC_VPOS_END() argument
270 return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK; in DSI_ACTIVE_VSYNC_VPOS_END()
281 static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val) in DSI_CMD_CFG0_DST_FORMAT() argument
283 return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK; in DSI_CMD_CFG0_DST_FORMAT()
290 static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val) in DSI_CMD_CFG0_INTERLEAVE_MAX() argument
292 return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK; in DSI_CMD_CFG0_INTERLEAVE_MAX()
296 static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val) in DSI_CMD_CFG0_RGB_SWAP() argument
298 return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK; in DSI_CMD_CFG0_RGB_SWAP()
304 static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val) in DSI_CMD_CFG1_WR_MEM_START() argument
306 return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK; in DSI_CMD_CFG1_WR_MEM_START()
310 static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val) in DSI_CMD_CFG1_WR_MEM_CONTINUE() argument
312 return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK; in DSI_CMD_CFG1_WR_MEM_CONTINUE()
323 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val) in DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE() argument
325 …return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MA… in DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE()
329 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val) in DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL() argument
331 …return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL… in DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL()
335 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val) in DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT() argument
337 …return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__… in DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT()
343 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val) in DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL() argument
345 return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK; in DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL()
349 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val) in DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL() argument
351 return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK; in DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL()
363 static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val) in DSI_TRIG_CTRL_DMA_TRIGGER() argument
365 return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK; in DSI_TRIG_CTRL_DMA_TRIGGER()
369 static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val) in DSI_TRIG_CTRL_MDP_TRIGGER() argument
371 return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK; in DSI_TRIG_CTRL_MDP_TRIGGER()
375 static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val) in DSI_TRIG_CTRL_STREAM() argument
377 return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK; in DSI_TRIG_CTRL_STREAM()
396 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val) in DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE() argument
398 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK; in DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE()
402 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) in DSI_CLKOUT_TIMING_CTRL_T_CLK_POST() argument
404 …return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MA… in DSI_CLKOUT_TIMING_CTRL_T_CLK_POST()
417 static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) in DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL() argument
419 return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK; in DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL()
449 static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) in DSI_RDBK_DATA_CTRL_COUNT() argument
451 return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK; in DSI_RDBK_DATA_CTRL_COUNT()
458 static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) in DSI_VERSION_MAJOR() argument
460 return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK; in DSI_VERSION_MAJOR()
599 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO() argument
601 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_… in DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO()
607 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL() argument
609 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL… in DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL()
615 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE() argument
617 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CT… in DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE()
625 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT() argument
627 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4… in DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT()
633 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO() argument
635 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5… in DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO()
641 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE() argument
643 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTR… in DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE()
649 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL() argument
651 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_… in DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL()
657 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST() argument
659 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8… in DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST()
665 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO() argument
667 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_T… in DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO()
671 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE() argument
673 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9… in DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE()
679 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET() argument
681 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1… in DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET()
687 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD() argument
689 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTR… in DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD()
840 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO() argument
842 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO… in DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO()
848 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL() argument
850 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRA… in DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL()
856 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE() argument
858 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_P… in DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE()
867 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT() argument
869 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__… in DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT()
875 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO() argument
877 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__… in DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO()
883 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE() argument
885 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PRE… in DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE()
891 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL() argument
893 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL… in DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL()
899 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST() argument
901 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__… in DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST()
907 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_9_TA_GO() argument
909 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK; in DSI_28nm_PHY_TIMING_CTRL_9_TA_GO()
913 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE() argument
915 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__… in DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE()
921 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_10_TA_GET() argument
923 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__… in DSI_28nm_PHY_TIMING_CTRL_10_TA_GET()
929 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD() argument
931 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3… in DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD()
1016 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val) in DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV() argument
1018 …return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MA… in DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV()
1025 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val) in DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET() argument
1027 …return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET… in DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET()
1031 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val) in DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN() argument
1033 …return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN… in DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN()
1039 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val) in DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0() argument
1041 …return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_… in DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0()
1047 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val) in DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8() argument
1049 …return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ… in DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8()
1167 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO() argument
1169 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO… in DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO()
1175 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL() argument
1177 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRA… in DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL()
1183 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE() argument
1185 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_P… in DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE()
1194 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT() argument
1196 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__… in DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT()
1202 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO() argument
1204 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__… in DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO()
1210 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE() argument
1212 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PRE… in DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE()
1218 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL() argument
1220 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL… in DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL()
1226 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST() argument
1228 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__… in DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST()
1234 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_9_TA_GO() argument
1236 return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK; in DSI_20nm_PHY_TIMING_CTRL_9_TA_GO()
1240 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE() argument
1242 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__… in DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE()
1248 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_10_TA_GET() argument
1250 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__… in DSI_20nm_PHY_TIMING_CTRL_10_TA_GET()
1256 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD() argument
1258 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3… in DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD()