162 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val)  in AXXX_CP_RB_CNTL_BUFSZ()  argument
164 	return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK;  in AXXX_CP_RB_CNTL_BUFSZ()
168 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val)  in AXXX_CP_RB_CNTL_BLKSZ()  argument
170 	return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK;  in AXXX_CP_RB_CNTL_BLKSZ()
174 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val)  in AXXX_CP_RB_CNTL_BUF_SWAP()  argument
176 	return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK;  in AXXX_CP_RB_CNTL_BUF_SWAP()
185 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)  in AXXX_CP_RB_RPTR_ADDR_SWAP()  argument
187 	return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK;  in AXXX_CP_RB_RPTR_ADDR_SWAP()
191 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)  in AXXX_CP_RB_RPTR_ADDR_ADDR()  argument
193 	return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;  in AXXX_CP_RB_RPTR_ADDR_ADDR()
209 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val)  in AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START()  argument
211 …return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1…  in AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START()
215 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val)  in AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START()  argument
217 …return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2…  in AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START()
221 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)  in AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START()  argument
223 …return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_S…  in AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START()
229 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val)  in AXXX_CP_MEQ_THRESHOLDS_MEQ_END()  argument
231 	return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK;  in AXXX_CP_MEQ_THRESHOLDS_MEQ_END()
235 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val)  in AXXX_CP_MEQ_THRESHOLDS_ROQ_END()  argument
237 	return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK;  in AXXX_CP_MEQ_THRESHOLDS_ROQ_END()
243 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val)  in AXXX_CP_CSQ_AVAIL_RING()  argument
245 	return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK;  in AXXX_CP_CSQ_AVAIL_RING()
249 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val)  in AXXX_CP_CSQ_AVAIL_IB1()  argument
251 	return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK;  in AXXX_CP_CSQ_AVAIL_IB1()
255 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val)  in AXXX_CP_CSQ_AVAIL_IB2()  argument
257 	return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK;  in AXXX_CP_CSQ_AVAIL_IB2()
263 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val)  in AXXX_CP_STQ_AVAIL_ST()  argument
265 	return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK;  in AXXX_CP_STQ_AVAIL_ST()
271 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val)  in AXXX_CP_MEQ_AVAIL_MEQ()  argument
273 	return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK;  in AXXX_CP_MEQ_AVAIL_MEQ()
279 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val)  in AXXX_SCRATCH_UMSK_UMSK()  argument
281 	return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK;  in AXXX_SCRATCH_UMSK_UMSK()
285 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)  in AXXX_SCRATCH_UMSK_SWAP()  argument
287 	return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK;  in AXXX_SCRATCH_UMSK_SWAP()
329 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val)  in AXXX_CP_CSQ_RB_STAT_RPTR()  argument
331 	return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK;  in AXXX_CP_CSQ_RB_STAT_RPTR()
335 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val)  in AXXX_CP_CSQ_RB_STAT_WPTR()  argument
337 	return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK;  in AXXX_CP_CSQ_RB_STAT_WPTR()
343 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val)  in AXXX_CP_CSQ_IB1_STAT_RPTR()  argument
345 	return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK;  in AXXX_CP_CSQ_IB1_STAT_RPTR()
349 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val)  in AXXX_CP_CSQ_IB1_STAT_WPTR()  argument
351 	return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK;  in AXXX_CP_CSQ_IB1_STAT_WPTR()
357 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val)  in AXXX_CP_CSQ_IB2_STAT_RPTR()  argument
359 	return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK;  in AXXX_CP_CSQ_IB2_STAT_RPTR()
363 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)  in AXXX_CP_CSQ_IB2_STAT_WPTR()  argument
365 	return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;  in AXXX_CP_CSQ_IB2_STAT_WPTR()