866 	enum pipe pipe;  in vlv_display_power_well_init()  local
876 	for_each_pipe(dev_priv->dev, pipe) {  in vlv_display_power_well_init()
877 		u32 val = I915_READ(DPLL(pipe));  in vlv_display_power_well_init()
880 		if (pipe != PIPE_A)  in vlv_display_power_well_init()
883 		I915_WRITE(DPLL(pipe), val);  in vlv_display_power_well_init()
958 	enum pipe pipe;  in vlv_dpio_cmn_power_well_disable()  local
962 	for_each_pipe(dev_priv, pipe)  in vlv_dpio_cmn_power_well_disable()
963 		assert_pll_disabled(dev_priv, pipe);  in vlv_dpio_cmn_power_well_disable()
1099 	enum pipe pipe;  in chv_dpio_cmn_power_well_enable()  local
1106 		pipe = PIPE_A;  in chv_dpio_cmn_power_well_enable()
1109 		pipe = PIPE_C;  in chv_dpio_cmn_power_well_enable()
1124 	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);  in chv_dpio_cmn_power_well_enable()
1127 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);  in chv_dpio_cmn_power_well_enable()
1130 		tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);  in chv_dpio_cmn_power_well_enable()
1132 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);  in chv_dpio_cmn_power_well_enable()
1139 		tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);  in chv_dpio_cmn_power_well_enable()
1141 		vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);  in chv_dpio_cmn_power_well_enable()
1189 	enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;  in assert_chv_phy_powergate()
1208 	val = vlv_dpio_read(dev_priv, pipe, reg);  in assert_chv_phy_powergate()
1312 	enum pipe pipe = power_well->data;  in chv_pipe_power_well_enabled()  local
1318 	state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);  in chv_pipe_power_well_enabled()
1323 	WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));  in chv_pipe_power_well_enabled()
1324 	enabled = state == DP_SSS_PWR_ON(pipe);  in chv_pipe_power_well_enabled()
1330 	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);  in chv_pipe_power_well_enabled()
1342 	enum pipe pipe = power_well->data;  in chv_set_pipe_power_well()  local
1346 	state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);  in chv_set_pipe_power_well()
1351 	((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)  in chv_set_pipe_power_well()
1357 	ctrl &= ~DP_SSC_MASK(pipe);  in chv_set_pipe_power_well()
1358 	ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);  in chv_set_pipe_power_well()