68 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
71 static void intel_power_well_enable(struct drm_i915_private *dev_priv,  in intel_power_well_enable()  argument
75 	power_well->ops->enable(dev_priv, power_well);  in intel_power_well_enable()
79 static void intel_power_well_disable(struct drm_i915_private *dev_priv,  in intel_power_well_disable()  argument
84 	power_well->ops->disable(dev_priv, power_well);  in intel_power_well_disable()
92 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,  in hsw_power_well_enabled()  argument
111 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,  in __intel_display_power_is_enabled()  argument
119 	if (dev_priv->pm.suspended)  in __intel_display_power_is_enabled()
122 	power_domains = &dev_priv->power_domains;  in __intel_display_power_is_enabled()
156 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,  in intel_display_power_is_enabled()  argument
162 	power_domains = &dev_priv->power_domains;  in intel_display_power_is_enabled()
165 	ret = __intel_display_power_is_enabled(dev_priv, domain);  in intel_display_power_is_enabled()
181 void intel_display_set_init_power(struct drm_i915_private *dev_priv,  in intel_display_set_init_power()  argument
184 	if (dev_priv->power_domains.init_power_on == enable)  in intel_display_set_init_power()
188 		intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);  in intel_display_set_init_power()
190 		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);  in intel_display_set_init_power()
192 	dev_priv->power_domains.init_power_on = enable;  in intel_display_set_init_power()
201 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)  in hsw_power_well_post_enable()  argument
203 	struct drm_device *dev = dev_priv->dev;  in hsw_power_well_post_enable()
220 		gen8_irq_power_well_post_enable(dev_priv,  in hsw_power_well_post_enable()
224 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,  in skl_power_well_post_enable()  argument
227 	struct drm_device *dev = dev_priv->dev;  in skl_power_well_post_enable()
244 		gen8_irq_power_well_post_enable(dev_priv,  in skl_power_well_post_enable()
249 		if (!dev_priv->power_domains.initializing)  in skl_power_well_post_enable()
251 		gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);  in skl_power_well_post_enable()
255 static void hsw_set_power_well(struct drm_i915_private *dev_priv,  in hsw_set_power_well()  argument
275 			hsw_power_well_post_enable(dev_priv);  in hsw_set_power_well()
382 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)  in assert_can_enable_dc9()  argument
384 	struct drm_device *dev = dev_priv->dev;  in assert_can_enable_dc9()
392 	WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");  in assert_can_enable_dc9()
403 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)  in assert_can_disable_dc9()  argument
405 	WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");  in assert_can_disable_dc9()
420 void bxt_enable_dc9(struct drm_i915_private *dev_priv)  in bxt_enable_dc9()  argument
424 	assert_can_enable_dc9(dev_priv);  in bxt_enable_dc9()
434 void bxt_disable_dc9(struct drm_i915_private *dev_priv)  in bxt_disable_dc9()  argument
438 	assert_can_disable_dc9(dev_priv);  in bxt_disable_dc9()
449 			struct drm_i915_private *dev_priv)  in gen9_set_dc_state_debugmask_memory_up()  argument
462 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)  in assert_can_enable_dc5()  argument
464 	struct drm_device *dev = dev_priv->dev;  in assert_can_enable_dc5()
465 	bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,  in assert_can_enable_dc5()
474 	WARN_ONCE(dev_priv->pm.suspended,  in assert_can_enable_dc5()
477 	assert_csr_loaded(dev_priv);  in assert_can_enable_dc5()
480 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)  in assert_can_disable_dc5()  argument
482 	bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,  in assert_can_disable_dc5()
488 	if (dev_priv->power_domains.initializing)  in assert_can_disable_dc5()
492 	WARN_ONCE(dev_priv->pm.suspended,  in assert_can_disable_dc5()
496 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)  in gen9_enable_dc5()  argument
500 	assert_can_enable_dc5(dev_priv);  in gen9_enable_dc5()
504 	gen9_set_dc_state_debugmask_memory_up(dev_priv);  in gen9_enable_dc5()
513 static void gen9_disable_dc5(struct drm_i915_private *dev_priv)  in gen9_disable_dc5()  argument
517 	assert_can_disable_dc5(dev_priv);  in gen9_disable_dc5()
527 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)  in assert_can_enable_dc6()  argument
529 	struct drm_device *dev = dev_priv->dev;  in assert_can_enable_dc6()
538 	assert_csr_loaded(dev_priv);  in assert_can_enable_dc6()
541 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)  in assert_can_disable_dc6()  argument
547 	if (dev_priv->power_domains.initializing)  in assert_can_disable_dc6()
550 	assert_csr_loaded(dev_priv);  in assert_can_disable_dc6()
555 static void skl_enable_dc6(struct drm_i915_private *dev_priv)  in skl_enable_dc6()  argument
559 	assert_can_enable_dc6(dev_priv);  in skl_enable_dc6()
563 	gen9_set_dc_state_debugmask_memory_up(dev_priv);  in skl_enable_dc6()
572 static void skl_disable_dc6(struct drm_i915_private *dev_priv)  in skl_disable_dc6()  argument
576 	assert_can_disable_dc6(dev_priv);  in skl_disable_dc6()
586 static void skl_set_power_well(struct drm_i915_private *dev_priv,  in skl_set_power_well()  argument
589 	struct drm_device *dev = dev_priv->dev;  in skl_set_power_well()
636 					skl_disable_dc6(dev_priv);  in skl_set_power_well()
642 					if (!dev_priv->power_domains.initializing)  in skl_set_power_well()
645 					gen9_disable_dc5(dev_priv);  in skl_set_power_well()
663 				(intel_csr_load_status_get(dev_priv) == FW_LOADED))  in skl_set_power_well()
678 				wait_for((state = intel_csr_load_status_get(dev_priv)) !=  in skl_set_power_well()
685 						skl_enable_dc6(dev_priv);  in skl_set_power_well()
687 						gen9_enable_dc5(dev_priv);  in skl_set_power_well()
705 		skl_power_well_post_enable(dev_priv, power_well);  in skl_set_power_well()
708 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,  in hsw_power_well_sync_hw()  argument
711 	hsw_set_power_well(dev_priv, power_well, power_well->count > 0);  in hsw_power_well_sync_hw()
721 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,  in hsw_power_well_enable()  argument
724 	hsw_set_power_well(dev_priv, power_well, true);  in hsw_power_well_enable()
727 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,  in hsw_power_well_disable()  argument
730 	hsw_set_power_well(dev_priv, power_well, false);  in hsw_power_well_disable()
733 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,  in skl_power_well_enabled()  argument
742 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,  in skl_power_well_sync_hw()  argument
745 	skl_set_power_well(dev_priv, power_well, power_well->count > 0);  in skl_power_well_sync_hw()
751 static void skl_power_well_enable(struct drm_i915_private *dev_priv,  in skl_power_well_enable()  argument
754 	skl_set_power_well(dev_priv, power_well, true);  in skl_power_well_enable()
757 static void skl_power_well_disable(struct drm_i915_private *dev_priv,  in skl_power_well_disable()  argument
760 	skl_set_power_well(dev_priv, power_well, false);  in skl_power_well_disable()
763 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,  in i9xx_always_on_power_well_noop()  argument
768 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,  in i9xx_always_on_power_well_enabled()  argument
774 static void vlv_set_power_well(struct drm_i915_private *dev_priv,  in vlv_set_power_well()  argument
786 	mutex_lock(&dev_priv->rps.hw_lock);  in vlv_set_power_well()
789 	((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)  in vlv_set_power_well()
794 	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);  in vlv_set_power_well()
797 	vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);  in vlv_set_power_well()
802 			  vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));  in vlv_set_power_well()
807 	mutex_unlock(&dev_priv->rps.hw_lock);  in vlv_set_power_well()
810 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,  in vlv_power_well_sync_hw()  argument
813 	vlv_set_power_well(dev_priv, power_well, power_well->count > 0);  in vlv_power_well_sync_hw()
816 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,  in vlv_power_well_enable()  argument
819 	vlv_set_power_well(dev_priv, power_well, true);  in vlv_power_well_enable()
822 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,  in vlv_power_well_disable()  argument
825 	vlv_set_power_well(dev_priv, power_well, false);  in vlv_power_well_disable()
828 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,  in vlv_power_well_enabled()  argument
840 	mutex_lock(&dev_priv->rps.hw_lock);  in vlv_power_well_enabled()
842 	state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;  in vlv_power_well_enabled()
856 	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;  in vlv_power_well_enabled()
859 	mutex_unlock(&dev_priv->rps.hw_lock);  in vlv_power_well_enabled()
864 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)  in vlv_display_power_well_init()  argument
876 	for_each_pipe(dev_priv->dev, pipe) {  in vlv_display_power_well_init()
886 	spin_lock_irq(&dev_priv->irq_lock);  in vlv_display_power_well_init()
887 	valleyview_enable_display_irqs(dev_priv);  in vlv_display_power_well_init()
888 	spin_unlock_irq(&dev_priv->irq_lock);  in vlv_display_power_well_init()
894 	if (dev_priv->power_domains.initializing)  in vlv_display_power_well_init()
897 	intel_hpd_init(dev_priv);  in vlv_display_power_well_init()
899 	i915_redisable_vga_power_on(dev_priv->dev);  in vlv_display_power_well_init()
902 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)  in vlv_display_power_well_deinit()  argument
904 	spin_lock_irq(&dev_priv->irq_lock);  in vlv_display_power_well_deinit()
905 	valleyview_disable_display_irqs(dev_priv);  in vlv_display_power_well_deinit()
906 	spin_unlock_irq(&dev_priv->irq_lock);  in vlv_display_power_well_deinit()
908 	vlv_power_sequencer_reset(dev_priv);  in vlv_display_power_well_deinit()
911 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,  in vlv_display_power_well_enable()  argument
916 	vlv_set_power_well(dev_priv, power_well, true);  in vlv_display_power_well_enable()
918 	vlv_display_power_well_init(dev_priv);  in vlv_display_power_well_enable()
921 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,  in vlv_display_power_well_disable()  argument
926 	vlv_display_power_well_deinit(dev_priv);  in vlv_display_power_well_disable()
928 	vlv_set_power_well(dev_priv, power_well, false);  in vlv_display_power_well_disable()
931 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,  in vlv_dpio_cmn_power_well_enable()  argument
939 	vlv_set_power_well(dev_priv, power_well, true);  in vlv_dpio_cmn_power_well_enable()
955 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,  in vlv_dpio_cmn_power_well_disable()  argument
962 	for_each_pipe(dev_priv, pipe)  in vlv_dpio_cmn_power_well_disable()
963 		assert_pll_disabled(dev_priv, pipe);  in vlv_dpio_cmn_power_well_disable()
968 	vlv_set_power_well(dev_priv, power_well, false);  in vlv_dpio_cmn_power_well_disable()
973 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,  in lookup_power_well()  argument
976 	struct i915_power_domains *power_domains = &dev_priv->power_domains;  in lookup_power_well()
990 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)  in assert_chv_phy_status()  argument
993 		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);  in assert_chv_phy_status()
995 		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);  in assert_chv_phy_status()
996 	u32 phy_control = dev_priv->chv_phy_control;  in assert_chv_phy_status()
1008 	if (!dev_priv->chv_phy_assert[DPIO_PHY0])  in assert_chv_phy_status()
1016 	if (!dev_priv->chv_phy_assert[DPIO_PHY1])  in assert_chv_phy_status()
1021 	if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {  in assert_chv_phy_status()
1062 	if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {  in assert_chv_phy_status()
1090 		     tmp, phy_status, dev_priv->chv_phy_control);  in assert_chv_phy_status()
1095 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,  in chv_dpio_cmn_power_well_enable()  argument
1115 	vlv_set_power_well(dev_priv, power_well, true);  in chv_dpio_cmn_power_well_enable()
1121 	mutex_lock(&dev_priv->sb_lock);  in chv_dpio_cmn_power_well_enable()
1124 	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);  in chv_dpio_cmn_power_well_enable()
1127 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);  in chv_dpio_cmn_power_well_enable()
1130 		tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);  in chv_dpio_cmn_power_well_enable()
1132 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);  in chv_dpio_cmn_power_well_enable()
1139 		tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);  in chv_dpio_cmn_power_well_enable()
1141 		vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);  in chv_dpio_cmn_power_well_enable()
1144 	mutex_unlock(&dev_priv->sb_lock);  in chv_dpio_cmn_power_well_enable()
1146 	dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);  in chv_dpio_cmn_power_well_enable()
1147 	I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);  in chv_dpio_cmn_power_well_enable()
1150 		      phy, dev_priv->chv_phy_control);  in chv_dpio_cmn_power_well_enable()
1152 	assert_chv_phy_status(dev_priv);  in chv_dpio_cmn_power_well_enable()
1155 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,  in chv_dpio_cmn_power_well_disable()  argument
1165 		assert_pll_disabled(dev_priv, PIPE_A);  in chv_dpio_cmn_power_well_disable()
1166 		assert_pll_disabled(dev_priv, PIPE_B);  in chv_dpio_cmn_power_well_disable()
1169 		assert_pll_disabled(dev_priv, PIPE_C);  in chv_dpio_cmn_power_well_disable()
1172 	dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);  in chv_dpio_cmn_power_well_disable()
1173 	I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);  in chv_dpio_cmn_power_well_disable()
1175 	vlv_set_power_well(dev_priv, power_well, false);  in chv_dpio_cmn_power_well_disable()
1178 		      phy, dev_priv->chv_phy_control);  in chv_dpio_cmn_power_well_disable()
1181 	dev_priv->chv_phy_assert[phy] = true;  in chv_dpio_cmn_power_well_disable()
1183 	assert_chv_phy_status(dev_priv);  in chv_dpio_cmn_power_well_disable()
1186 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,  in assert_chv_phy_powergate()  argument
1199 	if (!dev_priv->chv_phy_assert[phy])  in assert_chv_phy_powergate()
1207 	mutex_lock(&dev_priv->sb_lock);  in assert_chv_phy_powergate()
1208 	val = vlv_dpio_read(dev_priv, pipe, reg);  in assert_chv_phy_powergate()
1209 	mutex_unlock(&dev_priv->sb_lock);  in assert_chv_phy_powergate()
1248 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,  in chv_phy_powergate_ch()  argument
1251 	struct i915_power_domains *power_domains = &dev_priv->power_domains;  in chv_phy_powergate_ch()
1256 	was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);  in chv_phy_powergate_ch()
1262 		dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);  in chv_phy_powergate_ch()
1264 		dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);  in chv_phy_powergate_ch()
1266 	I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);  in chv_phy_powergate_ch()
1269 		      phy, ch, dev_priv->chv_phy_control);  in chv_phy_powergate_ch()
1271 	assert_chv_phy_status(dev_priv);  in chv_phy_powergate_ch()
1282 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in chv_phy_powergate_lanes()  local
1283 	struct i915_power_domains *power_domains = &dev_priv->power_domains;  in chv_phy_powergate_lanes()
1289 	dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);  in chv_phy_powergate_lanes()
1290 	dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);  in chv_phy_powergate_lanes()
1293 		dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);  in chv_phy_powergate_lanes()
1295 		dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);  in chv_phy_powergate_lanes()
1297 	I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);  in chv_phy_powergate_lanes()
1300 		      phy, ch, mask, dev_priv->chv_phy_control);  in chv_phy_powergate_lanes()
1302 	assert_chv_phy_status(dev_priv);  in chv_phy_powergate_lanes()
1304 	assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);  in chv_phy_powergate_lanes()
1309 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,  in chv_pipe_power_well_enabled()  argument
1316 	mutex_lock(&dev_priv->rps.hw_lock);  in chv_pipe_power_well_enabled()
1318 	state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);  in chv_pipe_power_well_enabled()
1330 	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);  in chv_pipe_power_well_enabled()
1333 	mutex_unlock(&dev_priv->rps.hw_lock);  in chv_pipe_power_well_enabled()
1338 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,  in chv_set_pipe_power_well()  argument
1348 	mutex_lock(&dev_priv->rps.hw_lock);  in chv_set_pipe_power_well()
1351 	((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)  in chv_set_pipe_power_well()
1356 	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);  in chv_set_pipe_power_well()
1359 	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);  in chv_set_pipe_power_well()
1364 			  vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));  in chv_set_pipe_power_well()
1369 	mutex_unlock(&dev_priv->rps.hw_lock);  in chv_set_pipe_power_well()
1372 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,  in chv_pipe_power_well_sync_hw()  argument
1377 	chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);  in chv_pipe_power_well_sync_hw()
1380 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,  in chv_pipe_power_well_enable()  argument
1385 	chv_set_pipe_power_well(dev_priv, power_well, true);  in chv_pipe_power_well_enable()
1387 	vlv_display_power_well_init(dev_priv);  in chv_pipe_power_well_enable()
1390 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,  in chv_pipe_power_well_disable()  argument
1395 	vlv_display_power_well_deinit(dev_priv);  in chv_pipe_power_well_disable()
1397 	chv_set_pipe_power_well(dev_priv, power_well, false);  in chv_pipe_power_well_disable()
1412 void intel_display_power_get(struct drm_i915_private *dev_priv,  in intel_display_power_get()  argument
1419 	intel_runtime_pm_get(dev_priv);  in intel_display_power_get()
1421 	power_domains = &dev_priv->power_domains;  in intel_display_power_get()
1427 			intel_power_well_enable(dev_priv, power_well);  in intel_display_power_get()
1444 void intel_display_power_put(struct drm_i915_private *dev_priv,  in intel_display_power_put()  argument
1451 	power_domains = &dev_priv->power_domains;  in intel_display_power_put()
1462 			intel_power_well_disable(dev_priv, power_well);  in intel_display_power_put()
1467 	intel_runtime_pm_put(dev_priv);  in intel_display_power_put()
1732 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,  in intel_display_power_well_is_enabled()  argument
1738 	power_well = lookup_power_well(dev_priv, power_well_id);  in intel_display_power_well_is_enabled()
1739 	ret = power_well->ops->is_enabled(dev_priv, power_well);  in intel_display_power_well_is_enabled()
1817 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,  in sanitize_disable_power_well_option()  argument
1823 	if (IS_SKYLAKE(dev_priv)) {  in sanitize_disable_power_well_option()
1843 int intel_power_domains_init(struct drm_i915_private *dev_priv)  in intel_power_domains_init()  argument
1845 	struct i915_power_domains *power_domains = &dev_priv->power_domains;  in intel_power_domains_init()
1847 	i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,  in intel_power_domains_init()
1858 	if (IS_HASWELL(dev_priv->dev)) {  in intel_power_domains_init()
1860 	} else if (IS_BROADWELL(dev_priv->dev)) {  in intel_power_domains_init()
1862 	} else if (IS_SKYLAKE(dev_priv->dev)) {  in intel_power_domains_init()
1864 	} else if (IS_BROXTON(dev_priv->dev)) {  in intel_power_domains_init()
1866 	} else if (IS_CHERRYVIEW(dev_priv->dev)) {  in intel_power_domains_init()
1868 	} else if (IS_VALLEYVIEW(dev_priv->dev)) {  in intel_power_domains_init()
1877 static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)  in intel_runtime_pm_disable()  argument
1879 	struct drm_device *dev = dev_priv->dev;  in intel_runtime_pm_disable()
1900 void intel_power_domains_fini(struct drm_i915_private *dev_priv)  in intel_power_domains_fini()  argument
1902 	intel_runtime_pm_disable(dev_priv);  in intel_power_domains_fini()
1907 	intel_display_set_init_power(dev_priv, true);  in intel_power_domains_fini()
1910 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)  in intel_power_domains_resume()  argument
1912 	struct i915_power_domains *power_domains = &dev_priv->power_domains;  in intel_power_domains_resume()
1918 		power_well->ops->sync_hw(dev_priv, power_well);  in intel_power_domains_resume()
1919 		power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,  in intel_power_domains_resume()
1925 static void chv_phy_control_init(struct drm_i915_private *dev_priv)  in chv_phy_control_init()  argument
1928 		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);  in chv_phy_control_init()
1930 		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);  in chv_phy_control_init()
1939 	dev_priv->chv_phy_control =  in chv_phy_control_init()
1953 	if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {  in chv_phy_control_init()
1961 			dev_priv->chv_phy_control |=  in chv_phy_control_init()
1964 		dev_priv->chv_phy_control |=  in chv_phy_control_init()
1971 			dev_priv->chv_phy_control |=  in chv_phy_control_init()
1974 		dev_priv->chv_phy_control |=  in chv_phy_control_init()
1977 		dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);  in chv_phy_control_init()
1979 		dev_priv->chv_phy_assert[DPIO_PHY0] = false;  in chv_phy_control_init()
1981 		dev_priv->chv_phy_assert[DPIO_PHY0] = true;  in chv_phy_control_init()
1984 	if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {  in chv_phy_control_init()
1993 			dev_priv->chv_phy_control |=  in chv_phy_control_init()
1996 		dev_priv->chv_phy_control |=  in chv_phy_control_init()
1999 		dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);  in chv_phy_control_init()
2001 		dev_priv->chv_phy_assert[DPIO_PHY1] = false;  in chv_phy_control_init()
2003 		dev_priv->chv_phy_assert[DPIO_PHY1] = true;  in chv_phy_control_init()
2006 	I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);  in chv_phy_control_init()
2009 		      dev_priv->chv_phy_control);  in chv_phy_control_init()
2012 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)  in vlv_cmnlane_wa()  argument
2015 		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);  in vlv_cmnlane_wa()
2017 		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);  in vlv_cmnlane_wa()
2020 	if (cmn->ops->is_enabled(dev_priv, cmn) &&  in vlv_cmnlane_wa()
2021 	    disp2d->ops->is_enabled(dev_priv, disp2d) &&  in vlv_cmnlane_wa()
2028 	disp2d->ops->enable(dev_priv, disp2d);  in vlv_cmnlane_wa()
2037 	cmn->ops->disable(dev_priv, cmn);  in vlv_cmnlane_wa()
2047 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)  in intel_power_domains_init_hw()  argument
2049 	struct drm_device *dev = dev_priv->dev;  in intel_power_domains_init_hw()
2050 	struct i915_power_domains *power_domains = &dev_priv->power_domains;  in intel_power_domains_init_hw()
2056 		chv_phy_control_init(dev_priv);  in intel_power_domains_init_hw()
2060 		vlv_cmnlane_wa(dev_priv);  in intel_power_domains_init_hw()
2065 	intel_display_set_init_power(dev_priv, true);  in intel_power_domains_init_hw()
2066 	intel_power_domains_resume(dev_priv);  in intel_power_domains_init_hw()
2080 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)  in intel_runtime_pm_get()  argument
2082 	struct drm_device *dev = dev_priv->dev;  in intel_runtime_pm_get()
2089 	WARN(dev_priv->pm.suspended, "Device still suspended.\n");  in intel_runtime_pm_get()
2109 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)  in intel_runtime_pm_get_noresume()  argument
2111 	struct drm_device *dev = dev_priv->dev;  in intel_runtime_pm_get_noresume()
2117 	WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");  in intel_runtime_pm_get_noresume()
2129 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)  in intel_runtime_pm_put()  argument
2131 	struct drm_device *dev = dev_priv->dev;  in intel_runtime_pm_put()
2151 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)  in intel_runtime_pm_enable()  argument
2153 	struct drm_device *dev = dev_priv->dev;  in intel_runtime_pm_enable()