1016 	if (!dev_priv->chv_phy_assert[DPIO_PHY1])  in assert_chv_phy_status()
1017 		phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |  in assert_chv_phy_status()
1018 				     PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |  in assert_chv_phy_status()
1019 				     PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));  in assert_chv_phy_status()
1063 		phy_status |= PHY_POWERGOOD(DPIO_PHY1);  in assert_chv_phy_status()
1066 		if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)  in assert_chv_phy_status()
1067 			phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);  in assert_chv_phy_status()
1070 			     PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))  in assert_chv_phy_status()
1071 			phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);  in assert_chv_phy_status()
1074 			     PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))  in assert_chv_phy_status()
1075 			phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);  in assert_chv_phy_status()
1077 			     PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))  in assert_chv_phy_status()
1078 			phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);  in assert_chv_phy_status()
1110 		phy = DPIO_PHY1;  in chv_dpio_cmn_power_well_enable()
1168 		phy = DPIO_PHY1;  in chv_dpio_cmn_power_well_disable()
1941 		PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |  in chv_phy_control_init()
1944 		PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);  in chv_phy_control_init()
1994 				PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);  in chv_phy_control_init()
1997 			PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);  in chv_phy_control_init()
1999 		dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);  in chv_phy_control_init()
2001 		dev_priv->chv_phy_assert[DPIO_PHY1] = false;  in chv_phy_control_init()
2003 		dev_priv->chv_phy_assert[DPIO_PHY1] = true;  in chv_phy_control_init()