Lines Matching refs:BIT
126 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { in __intel_display_power_is_enabled()
288 BIT(POWER_DOMAIN_TRANSCODER_A) | \
289 BIT(POWER_DOMAIN_PIPE_B) | \
290 BIT(POWER_DOMAIN_TRANSCODER_B) | \
291 BIT(POWER_DOMAIN_PIPE_C) | \
292 BIT(POWER_DOMAIN_TRANSCODER_C) | \
293 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
294 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
295 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
296 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
297 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
298 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
299 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
300 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
301 BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
302 BIT(POWER_DOMAIN_AUX_B) | \
303 BIT(POWER_DOMAIN_AUX_C) | \
304 BIT(POWER_DOMAIN_AUX_D) | \
305 BIT(POWER_DOMAIN_AUDIO) | \
306 BIT(POWER_DOMAIN_VGA) | \
307 BIT(POWER_DOMAIN_INIT))
310 BIT(POWER_DOMAIN_PLLS) | \
311 BIT(POWER_DOMAIN_PIPE_A) | \
312 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
313 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
314 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
315 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
316 BIT(POWER_DOMAIN_AUX_A) | \
317 BIT(POWER_DOMAIN_INIT))
319 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
320 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
321 BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
322 BIT(POWER_DOMAIN_INIT))
324 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
325 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
326 BIT(POWER_DOMAIN_INIT))
328 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
329 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
330 BIT(POWER_DOMAIN_INIT))
332 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
333 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
334 BIT(POWER_DOMAIN_INIT))
337 BIT(POWER_DOMAIN_PLLS) | \
338 BIT(POWER_DOMAIN_INIT))
347 BIT(POWER_DOMAIN_INIT))
350 BIT(POWER_DOMAIN_TRANSCODER_A) | \
351 BIT(POWER_DOMAIN_PIPE_B) | \
352 BIT(POWER_DOMAIN_TRANSCODER_B) | \
353 BIT(POWER_DOMAIN_PIPE_C) | \
354 BIT(POWER_DOMAIN_TRANSCODER_C) | \
355 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
356 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
357 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
358 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
359 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
360 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
361 BIT(POWER_DOMAIN_AUX_B) | \
362 BIT(POWER_DOMAIN_AUX_C) | \
363 BIT(POWER_DOMAIN_AUDIO) | \
364 BIT(POWER_DOMAIN_VGA) | \
365 BIT(POWER_DOMAIN_GMBUS) | \
366 BIT(POWER_DOMAIN_INIT))
369 BIT(POWER_DOMAIN_PIPE_A) | \
370 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
371 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
372 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
373 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
374 BIT(POWER_DOMAIN_AUX_A) | \
375 BIT(POWER_DOMAIN_PLLS) | \
376 BIT(POWER_DOMAIN_INIT))
380 BIT(POWER_DOMAIN_INIT))
971 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1425 for_each_power_well(i, power_well, BIT(domain), power_domains) { in intel_display_power_get()
1458 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { in intel_display_power_put()
1471 BIT(POWER_DOMAIN_PIPE_A) | \
1472 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
1473 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
1474 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
1475 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1476 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1477 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1478 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1479 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
1480 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
1481 BIT(POWER_DOMAIN_PORT_CRT) | \
1482 BIT(POWER_DOMAIN_PLLS) | \
1483 BIT(POWER_DOMAIN_AUX_A) | \
1484 BIT(POWER_DOMAIN_AUX_B) | \
1485 BIT(POWER_DOMAIN_AUX_C) | \
1486 BIT(POWER_DOMAIN_AUX_D) | \
1487 BIT(POWER_DOMAIN_GMBUS) | \
1488 BIT(POWER_DOMAIN_INIT))
1491 BIT(POWER_DOMAIN_INIT))
1495 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1498 BIT(POWER_DOMAIN_INIT))
1500 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
1504 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1505 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1506 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1507 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1508 BIT(POWER_DOMAIN_PORT_CRT) | \
1509 BIT(POWER_DOMAIN_AUX_B) | \
1510 BIT(POWER_DOMAIN_AUX_C) | \
1511 BIT(POWER_DOMAIN_INIT))
1514 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1515 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1516 BIT(POWER_DOMAIN_AUX_B) | \
1517 BIT(POWER_DOMAIN_INIT))
1520 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1521 BIT(POWER_DOMAIN_AUX_B) | \
1522 BIT(POWER_DOMAIN_INIT))
1525 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1526 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1527 BIT(POWER_DOMAIN_AUX_C) | \
1528 BIT(POWER_DOMAIN_INIT))
1531 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1532 BIT(POWER_DOMAIN_AUX_C) | \
1533 BIT(POWER_DOMAIN_INIT))
1536 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1537 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1538 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1539 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1540 BIT(POWER_DOMAIN_AUX_B) | \
1541 BIT(POWER_DOMAIN_AUX_C) | \
1542 BIT(POWER_DOMAIN_INIT))
1545 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
1546 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
1547 BIT(POWER_DOMAIN_AUX_D) | \
1548 BIT(POWER_DOMAIN_INIT))