146 struct  intel_engine_cs {  struct
147 	const char	*name;
148 	enum intel_ring_id {
174 	bool __must_check (*irq_get)(struct intel_engine_cs *ring);  argument
175 	void		(*irq_put)(struct intel_engine_cs *ring);  argument
177 	int		(*init_hw)(struct intel_engine_cs *ring);  argument
181 	void		(*write_tail)(struct intel_engine_cs *ring,  argument
193 	u32		(*get_seqno)(struct intel_engine_cs *ring,  argument
195 	void		(*set_seqno)(struct intel_engine_cs *ring,  argument
203 	void		(*cleanup)(struct intel_engine_cs *ring);  argument
257 				   struct intel_engine_cs *from,  argument
262 	} semaphore;
265 	spinlock_t execlist_lock;
266 	struct list_head execlist_queue;
267 	struct list_head execlist_retired_req_list;
268 	u8 next_context_status_buffer;
269 	u32             irq_keep_mask; /* bitmask for interrupts that should not be masked */
270 	int		(*emit_request)(struct drm_i915_gem_request *request);
271 	int		(*emit_flush)(struct drm_i915_gem_request *request,
274 	int		(*emit_bb_start)(struct drm_i915_gem_request *req,
287 	struct list_head active_list;
293 	struct list_head request_list;
300 	u32 last_submitted_seqno;
302 	bool gpu_caches_dirty;
304 	wait_queue_head_t irq_queue;
306 	struct intel_context *default_context;
307 	struct intel_context *last_context;
309 	struct intel_ring_hangcheck hangcheck;
311 	struct {
315 	} scratch;
317 	bool needs_cmd_parser;
351 bool intel_ring_initialized(struct intel_engine_cs *ring);  argument