1229 	struct intel_engine_cs *signaller = signaller_req->ring;  in gen8_rcs_signal()  local
1230 	struct drm_device *dev = signaller->dev;  in gen8_rcs_signal()
1245 		u64 gtt_offset = signaller->semaphore.signal_ggtt[i];  in gen8_rcs_signal()
1250 		intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));  in gen8_rcs_signal()
1251 		intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |  in gen8_rcs_signal()
1254 		intel_ring_emit(signaller, lower_32_bits(gtt_offset));  in gen8_rcs_signal()
1255 		intel_ring_emit(signaller, upper_32_bits(gtt_offset));  in gen8_rcs_signal()
1256 		intel_ring_emit(signaller, seqno);  in gen8_rcs_signal()
1257 		intel_ring_emit(signaller, 0);  in gen8_rcs_signal()
1258 		intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |  in gen8_rcs_signal()
1260 		intel_ring_emit(signaller, 0);  in gen8_rcs_signal()
1270 	struct intel_engine_cs *signaller = signaller_req->ring;  in gen8_xcs_signal()  local
1271 	struct drm_device *dev = signaller->dev;  in gen8_xcs_signal()
1286 		u64 gtt_offset = signaller->semaphore.signal_ggtt[i];  in gen8_xcs_signal()
1291 		intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |  in gen8_xcs_signal()
1293 		intel_ring_emit(signaller, lower_32_bits(gtt_offset) |  in gen8_xcs_signal()
1295 		intel_ring_emit(signaller, upper_32_bits(gtt_offset));  in gen8_xcs_signal()
1296 		intel_ring_emit(signaller, seqno);  in gen8_xcs_signal()
1297 		intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |  in gen8_xcs_signal()
1299 		intel_ring_emit(signaller, 0);  in gen8_xcs_signal()
1308 	struct intel_engine_cs *signaller = signaller_req->ring;  in gen6_signal()  local
1309 	struct drm_device *dev = signaller->dev;  in gen6_signal()
1324 		u32 mbox_reg = signaller->semaphore.mbox.signal[i];  in gen6_signal()
1327 			intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));  in gen6_signal()
1328 			intel_ring_emit(signaller, mbox_reg);  in gen6_signal()
1329 			intel_ring_emit(signaller, seqno);  in gen6_signal()
1335 		intel_ring_emit(signaller, MI_NOOP);  in gen6_signal()
1388 	       struct intel_engine_cs *signaller,  in gen8_ring_sync()  argument
1405 			lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));  in gen8_ring_sync()
1407 			upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));  in gen8_ring_sync()
1414 	       struct intel_engine_cs *signaller,  in gen6_ring_sync()  argument
1421 	u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];  in gen6_ring_sync()