220 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in intel_emit_post_sync_nonzero_flush()  local
230 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */  in intel_emit_post_sync_nonzero_flush()
242 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */  in intel_emit_post_sync_nonzero_flush()
257 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in gen6_render_ring_flush()  local
297 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);  in gen6_render_ring_flush()
330 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in gen7_render_ring_flush()  local
381 	intel_ring_emit(ring, scratch_addr);  in gen7_render_ring_flush()
390 		       u32 flags, u32 scratch_addr)  in gen8_emit_pipe_control()  argument
401 	intel_ring_emit(ring, scratch_addr);  in gen8_emit_pipe_control()
415 	u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in gen8_render_ring_flush()  local
445 	return gen8_emit_pipe_control(req, flags, scratch_addr);  in gen8_render_ring_flush()
1466 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in pc_render_add_request()  local
1487 	PIPE_CONTROL_FLUSH(ring, scratch_addr);  in pc_render_add_request()
1488 	scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */  in pc_render_add_request()
1489 	PIPE_CONTROL_FLUSH(ring, scratch_addr);  in pc_render_add_request()
1490 	scratch_addr += 2 * CACHELINE_BYTES;  in pc_render_add_request()
1491 	PIPE_CONTROL_FLUSH(ring, scratch_addr);  in pc_render_add_request()
1492 	scratch_addr += 2 * CACHELINE_BYTES;  in pc_render_add_request()
1493 	PIPE_CONTROL_FLUSH(ring, scratch_addr);  in pc_render_add_request()
1494 	scratch_addr += 2 * CACHELINE_BYTES;  in pc_render_add_request()
1495 	PIPE_CONTROL_FLUSH(ring, scratch_addr);  in pc_render_add_request()
1496 	scratch_addr += 2 * CACHELINE_BYTES;  in pc_render_add_request()
1497 	PIPE_CONTROL_FLUSH(ring, scratch_addr);  in pc_render_add_request()